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參數(shù)資料
| 型號(hào)： | M37540M4-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 48/64頁(yè) |
| 文件大?。?/td> | 668K |
| 代理商： | M37540M4-XXXSP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
48
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timing Requirements (General purpose)
Table 11 Timing requirements (1) (V
CC
= 4.0 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min.
2
125
50
50
200
80
80
200
80
80
2000
950
950
400
200
1000
400
400
200
200
Typ.
Max.
Symbol
Parameter
Limits
Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR
0
input cycle time
CNTR
0
, INT
0
, INT
1
, input “H” pulse width
CNTR
0
, INT
0
, INT
1
, input “L” pulse width
CNTR
1
input cycle time
CNTR
1
input “H” pulse width
CNTR
1
input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
t
W
(RESET)
t
C
(X
IN
)
t
WH
(X
IN
)
t
WL
(X
IN
)
t
C
(CNTR
0
)
t
WH
(CNTR
0
)
t
WL
(CNTR
0
)
t
C
(CNTR
1
)
t
WH
(CNTR
1
)
t
WL
(CNTR
1
)
t
C
(S
CLK1
)
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
su
(RxD
1
–S
CLK1
)
t
h
(RxD
1
–S
CLK1
)
t
C
(S
CLK2
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
su
(S
DATA2
–S
CLK2
)
t
h
(S
CLK2
–S
DATA2
)
Note:
In this time, bit 6 of the serial I/O1 control register (address 001A
16
) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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