參數(shù)資料
型號(hào)： M37540M4-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 18/64頁(yè)
文件大?。?/td> 668K
代理商： M37540M4-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timers
The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y and
timer Z.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the inter-
rupt request bit corresponding to each timer is set to “1”.
G
Timer 1
Prescaler 1 always counts f(X
IN
)/16. Timer 1 always counts the
prescaler 1 output and periodically sets the interrupt request bit.
G
Timer A
Timer A is a 16-bit timer that can be selected in one of four modes.
Timer Mode
The timer counts f(X
IN
)/16.
Period Measurement Mode
CNTR
1
interrupt request is generated at rising/falling edge of
CNTR
1
pin input signal. Simultaneously, the value in timer A latch
is reloaded in timer A and timer A continues counting down. Ex-
cept for the above-mentioned, the operation in period measure-
ment mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR
1
pin input signal is retained until the timer A is read once after the
reload.
The rising/falling timing of CNTR
1
pin input signal is found by CNTR
1
interrupt.
Event Counter Mode
The timer counts signals input through the CNTR
1
pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
Pulse Width HL Continuously Measure-ment Mode
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
I
Note
G
CNTR
1
interrupt active edge selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR
1
interrupt request is generated at both rising and
falling edges of CNTR
1
pin input signal regardless of the setting of
CNTR
1
active edge switch bit.
Fig. 19 Structure of timer A mode register
Timer A mode register
(TAM : address 001D
16
)
b7
b0
Not used (return “0” when read)
Timer A operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR
1
active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR
1
interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
1
interrupt
Timer A stop control bit
0 : Count start
1 : Count stop
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