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參數(shù)資料
| 型號： | M37540M4-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 31/64頁 |
| 文件大?。?/td> | 668K |
| 代理商： | M37540M4-XXXSP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7540 Group
MITSUBISHI MICROCOMPUTERS
31
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
G
Serial I/O2
The serial I/O2 function can be used only for clock synchronous se-
rial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
Note: Serial I/O2 can be used in the following cases;
(1) Serial I/O1 is not used,
(2) Serial I/O1 is used as UART and BRG output divided by 16 is
selected as the synchronized clock.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
Set “0” to bit 3 to receive.
At reception, clear bit 7 to “0” by writing a dummy data to the serial
I/O2 register after completion of shift.
Fig. 32 Structure of serial I/O2 control registers
Fig. 33 Block diagram of serial I/O2
Internal synchronous clock selection bits
000 : f(X
IN
)/8
001 : f(X
IN
)/16
010 : f(X
IN
)/32
011 : f(X
IN
)/64
110 : f(X
IN
)/128
111 : f(X
IN
)/256
S
DATA2
pin selection bit (Note)
0 : I/O port / S
DATA2
input
1 : S
DATA2
output
b7 b0
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
S
CLK2
pin selection bit
0 : External clock (S
CLK2
is an input)
1 : Internal clock (S
CLK2
is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note :
When using it as a S
DATA
input, set the port P1
3
direction register to “0”.
Serial I/O2 control register
(SIO2CON: address 0030
16
)
“1”
“0”
“0”
“1”
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
X
IN
Data bus
Serial I/O2
interrupt request
S
DATA2
pin selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
S
CLK2
pin selection bit
Internal synchronous
clock selection bits
D
P1
2
/S
CLK2
P1
3
/S
DATA2
P1
2
latch
S
CLK2 pin
selection bit
S
CLK
P1
3
latch
S
DATA2
pin selection bit
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