參數(shù)資料
型號(hào)： M37281MAH-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-52
文件頁數(shù)： 130/172頁
文件大?。?/td> 1319K
代理商： M37281MAH-XXXSP
M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP
Rev.1.01
2003.07.16
page 60 of 170
8.10.6 Data Slice Line Specification Circuit
(1) Specification of Data Slice Line
This circuit decides a line on which caption data is superimposed.
The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2
line for a period of 1 field), and both fields (F1 and F2) are sliced
their data. The caption position register (address 00E616) is used
for each setting (refer to Table 8.10.1).
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position
register (at setting only 1 appropriate line). Figure 8.10.8 shows
the signals in the vertical blanking interval. Figure 8.10.9 shows
the structure of the caption position register.
(2) Specification of Line to Set Slice Voltage
The reference voltage for slicing (slice voltage) is generated for
the clock run-in pulse in the particular line (refer to Table 8.10.1).
The field to generate slice voltage is specified by bit 1 of data
slicer control register 1. The line to generate slice voltage 1 field is
specified by bits 6, 7 of the caption position register (refer to
Table 8.10.1).
Fig. 8.10.8 Signals in Vertical Blanking Interval
Video signal
Vertical blanking interval
Composite
video signal
Count value to be set in the caption position register (“0F16” in this case)
Hsep
Vsep
Hsep
Magnified drawing
Clock run-in
Start bit + 16-bit data
Start bit
Window for
deteminating
clock-run-in
Composite video
signal
Line 21
1 appropriate line is set by
the caption position register
(when setting line 19)
(3) Field Determination
The field determination flag can be read out by bit 3 of data slicer
control register 2. This flag charge at the falling edge of Vsep.
相關(guān)PDF資料
PDF描述
M37281EKSP 8-BIT, OTPROM, 8.1 MHz, MICROCONTROLLER, PDIP52
M37281MFH-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
M37281MAH-XXXSP 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP52
M37281MKH-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
M37281MAH-XXXSP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP52
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37281MFH-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
M37281MKH-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
M372899234 制造商:ITW Switches 功能描述:IN-RUSH
M372F3200DJ3-C 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V
M372F3280DJ3-C 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:32M x 72 DRAM DIMM with ECC Using 16Mx4, 4K & 8K Refresh, 3.3V
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