參數(shù)資料
型號(hào): M364E0883CJ0-C50
元件分類: DRAM
英文描述: 8M X 64 EDO DRAM MODULE, 50 ns, DMA168
封裝: DIMM-168
文件頁(yè)數(shù): 20/22頁(yè)
文件大?。?/td> 472K
代理商: M364E0883CJ0-C50
DRAM MODULE
M364E080(8)3CJ(T)0-C
AC CHARACTERISTICS (0
°C≤TA≤70°C, VCC=5.0V±10%. See notes 1,2.)
Parameter
Symbol
-50
-60
Unit
Note
Min
Max
Min
Max
Column address to W delay time
tAWD
48
53
ns
7
CAS precharge time to W delay time
tCPWD
53
60
ns
CAS setup time(CAS-before-RAS refresh)
tCSR
10
ns
13
CAS hold time(CAS-before-RAS refresh)
tCHR
8
ns
13
RAS to CAS precharge time
tRPC
3
ns
13
Access time from CAS precharge
tCPA
33
40
ns
3,13
Hyper page cycle time
tHPC
20
25
ns
12
Hyper page read-modify-write cycle time
tHPRWC
70
77
ns
12
CAS precharge time(Hyper page cycle)
tCP
8
10
ns
RAS pulse width (Hyper page cycle)
tRASP
50
200K
60
200K
ns
RAS hold time from CAS precharge
tRHCP
35
40
ns
13
W to RAS precharge time(C-B-R refresh)
tWRP
15
ns
13
W to RAS hold time(C-B-R refresh)
tWRH
8
ns
13
OE access time
tOEA
18
20
ns
13
OE to data delay
tOED
18
ns
13
Output buffer turn off delay time from OE
tOEZ
8
18
8
18
ns
13
OE command hold time
tOEH
13
15
ns
Output data hold time(C-B-R refresh)
tDOH
10
ns
13
Output buffer turn off delay time from RAS
tREZ
3
15
3
15
ns
6,11
Output buffer turn off delay time from W
tWEZ
8
18
8
20
ns
6,13
W to data delay
tWED
20
ns
13
OE to CAS hold time
tOCH
5
ns
CAS hold time to OE
tCHO
5
ns
OE precharge time
tOEP
5
ns
W pulse width (Hyper page cycle)
tWPE
5
ns
PDE to Valid PD bit
tPD
10
ns
PDE to PD bit Inactive
tPDOFF
2
7
2
7
ns
Present Detect Read Cycle
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