參數(shù)資料
型號(hào): M364E0883CJ0-C50
元件分類: DRAM
英文描述: 8M X 64 EDO DRAM MODULE, 50 ns, DMA168
封裝: DIMM-168
文件頁(yè)數(shù): 18/22頁(yè)
文件大小: 472K
代理商: M364E0883CJ0-C50
DRAM MODULE
M364E080(8)3CJ(T)0-C
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time,
tHPC.
ABSOLUTE MAXIMUM RATINGS *
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
Item
Symbol
Rating
Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
Power Dissipation
Short Circuit Output Current
VIN, VOUT
VCC
Tstg
PD
IOS
-1 to +7.0
-55 to +125
8
50
V
°C
W
mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70
°C)
*1 : VCC+2.0V at pulse width
≤20ns, which is measured at VCC.
*2 : -2.0V at pulse width
≤20ns, which is measured at VSS.
Item
Symbol
Min
Typ
Max
Unit
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
4.5
0
2.4
-1.0*2
5.0
0
-
5.5
0
VCC*1
0.8
V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
ICC1*
ICC2
ICC3*
ICC4*
ICC5
ICC6*
I(IL)
I(OL)
VOH
VOL
Symbol
Speedl
M364E0803CJ(T)0
M364E0883CJ(T)0
Unit
Min
Max
Min
Max
ICC1
-50
-60
-
960
880
-
720
640
mA
ICC2
Don
′t care
-
100
-
100
mA
ICC3
-50
-60
-
960
880
-
720
640
mA
ICC4
-50
-60
-
880
800
-
800
720
mA
ICC5
Don
′t care
-
30
-
30
mA
ICC6
-50
-60
-
960
880
-
720
640
mA
II(L)
IO(L)
Don
′t care
-10
-5
10
5
-10
-5
10
5
uA
VOH
VOL
Don
′t care
2.4
-
0.4
2.4
-
0.4
V
: Operating Current * (RAS, CAS, Address cycling @
tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @
tRC=min)
: Extended Data Out Mode Current * (RAS=VIL, CAS cycling :
tHPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
tRC=min)
: Input Leakage Current (Any input 0
≤VIN≤Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V
≤VOUT Vcc)
: Output High Voltage Level (IOH = -5mA)
: Output Low Voltage Level (IOL = 4.2mA)
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