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Rev.1.02
Nov 26, 2008
REJ03B0224-0102
455A Group
Fig 56. State transition
Fig 57. Set source and clear source of the P flag
Fig 58. Start condition identified example using the
SNZP instruction
Key-on wakeup
(Stabilizing time [d] )
F
RAM back-up
mode
f(HSOCO): stop
f(XIN): stop
f(XCIN): stop
f(LSOCO): stop
EPOF + POF2
instruction execution
Key-on wakeup
(Stabilizing time [c] )
B
Operation state
Operation source clock: f(XIN)
Ceramic resonator
D
Operation state
Operation source clock: f(LSOCO)
Low-spped on-chip oscillator
High-speed mode
EPOF + POF2
instruction execution
Key-on wakeup
(Stabilizing time [e] )
E
Clock operating mode
f(HSOCO): stop
f(XIN): stop
f(XCIN),
f(LSOCO):
by RG register
EPOF + POF
instruction execution
Key-on wakeup
Timer 3 underflow
(Stabilizing time [c] )
EPOF + POF
instruction execution
Key-on wakeup
Timer 3 underflow
(Stabilizing time [e] )
MR1, MR0
← 11
MR1, MR0
← 10
C
Operation state
Operation source clock: f(XCIN)
Quartz-crystal oscillation
EPOF + POF2
instruction execution
EPOF + POF
instruction execution
Key-on wakeup
Timer 3 underflow
(Stabilizing time [d] )
MR1, MR0
← 10
MR1, MR0
← 00
A
Operation state
Operation source clock:
f(HSOCO)
High-speed on-chip oscillator
EPOF + POF2
instruction execution
Key-on wakeup
(Stabilizing time [b] )
EPOF + POF
instruction execution
Key-on wakeup
Timer 3 underflow
(Stabilizing time [b] )
(Stabilizing time [a] )
MR1, MR0
← 00
MR1, MR0
← 01
MR
1
,MR
0
←
11
MR
1
,MR
0
←
01
MR
1
,M
R
0
←
11
MR
1
,MR0
←
00
Internal mode
Low-speed mode
M
R
1,
M
R
0
←
10
MR
1
,MR
0
←
01
Internal low-speed mode
Res
e
t
1. The system clock selected by the clock control registers MR and RG is retained at power down.
The oscillation stability time at return can be adjusted by setting the clock control registers MR and RG before transiting to
the power down state.
2. To transmit to the clock operating mode, the EPOF and POF instructions must be executed continuously.
3. To transmit to the RAM back-up mode, the EPOF and POF2 instructions must be executed continuously.
4. After reset release, the main clock (f(XIN)), the sub-clock, and the internal clock (f(HSOCO)) are enabled.
5. To select a stopped clock as the system clock, first start the clock selected by the clock control register RG and generate
the oscillation stability time by software. Then switch the system clock.
Stabilizing time [a] : Microcomputer starts its operation after counting the f(HSOCO) to 1376 times.
Stabilizing time [b] : Microcomputer starts its operation after counting the f(HSOCO) to (system clock division ratio X 15) times.
Stabilizing time [c] : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.
Stabilizing time [d] : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio X 171) times.
Stabilizing time [e] : Microcomputer starts its operation after counting the f(LSOCO) to (system clock division ratio X 15) times.
Notes
S
R
Q
Power downflagP
POF or
POF2
instruction
Reset input
Set source
Clear source
System reset
EPOF instruction +
POF or
POF2
instruction
EPOF instruction +
P
Program start
P= “1”
?
Warm start
Cold start
No
T3F =
?
Return from
timer 3 underflow
Return from
external wakeup signal
“1”
Yes
No
SNZT3
instruction
SNZP
instruction