參數(shù)資料
型號： M34518M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù)： 113/157頁
文件大?。?/td> 1783K
代理商： M34518M4-XXXFP
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 4
MCU Control Function
4 – 14
4.3.3.3
Note on Return Operation from STOP/HALT Mode
The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of
the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to
IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt.
For details of PSW and the IE and IRQ registers, see “nX-U8/100 Core Instruction Manual” and Chapter 5, “Interrupt”,
respectively.
Table 4-1 and Table 4-2 show the return operations from STOP/HALT mode.
Table 4-1
Return Operation from STOP/HALT Mode (Non-Maskable Interrupt)
ELEVEL
MIE
IEn.m
IRQn.m
Return operation from STOP/HALT mode
*
0
Not returned from STOP/HALT mode.
3
*
1
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. The program operation does not go to the
interrupt routine.
0, 1, 2
*
1
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
Table 4-2
Return Operation from STOP/HALT Mode (Maskable Interrupt)
ELEVEL
MIE
IEn.m
IRQn.m
Return operation from STOP/HALT mode
*
0
*
0
1
Not returned from STOP/HALT mode.
*
0
1
2,3
1
After the mode is returned from STOP/HALT mode, the program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”. The program operation does not go to the
interrupt routine.
0, 1
1
After the mode is returned from the STOP/HALT mode, program
operation restarts from the instruction following the instruction that
sets the STP/HLT bit to “1”, then goes to the interrupt routine.
Notes:
If the ELEVEL bit is 0H, it indicates that the CPU is performing neither nonmaskable interrupt processing nor
maskable interrupt processing nor software interrupt processing.
If the ELEVEL bit is 1H, it indicates that the CPU is performing maskable interrupt processing or software interrupt
processing. (ELEVEL is set during interrupt transition cycle.)
If the ELEVEL bit is 2H, it indicates that the CPU is performing non-maskable interrupt processing. (ELEVEL is set
during interrupt transition cycle.)
If the ELEVEL bit is 3H, it indicates that the CPU is performing interrupt processing specific to the emulator. This
setting is not allowed in normal applications.
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相關代理商/技術參數(shù)
參數(shù)描述
M34518M4-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34518M6-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34518M8-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
M34519E8FP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES
M34519M6-XXXFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES
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