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參數(shù)資料
| 型號： | M34286G2GP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20 |
| 文件頁數(shù)： | 45/66頁 |
| 文件大小： | 495K |
| 代理商： | M34286G2GP |
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Rev.1.00
Aug 06, 2008
page 5 of 64
REJ03B0251-0100
4286 Group
CONNECTIONS OF UNUSED PINS
(Note when connecting to VSS and VDD)
Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Control
bits
1 bit
Output:
2 bits
Input:
3 bits
4 bits
1 bit
Control
instructions
SD
RD
CLD
SZD
OEA
IAE
OGA
IAG
SCAR
RCAR
Control
registers
PU1, PU2
PU0
Output structure
P-channel open-drain
CMOS
Input/
Output
I/O
(8)
I/O
(2)
Input
(1)
I/O
(4)
Output
(1)
Remark
Pull-down function and
key-on wakeup function
(programmable)
Pull-down function and
key-on wakeup function
(programmable)
Pull-down function and
key-on wakeup function
(programmable)
Pin
D0–D7
E0
E1
E2
G0–G3
CARR
Port
Port D
Port E
Port G
Port CARR
DEFINITION OF CLOCK AND CYCLE
System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the
Oscillation dividing instruction.
CCK, CCK2, or CCK4 instruction can be executed only once.
After one of their instruction is executed once, the operation is
same as the NOP instruction though the same or another
frequency dividing instruction is executed.
The system clock returns to its initial state (f(XIN)/8) when
system is returnd from RAM back-up mode.
Pin
D0–D7
E0, E1
E2
G0–G3
CARR
Connection
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open.
Connect to VSS.
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open.
Usage condition
Pull-down transistor OFF.
System clock
f(XIN)/8
f(XIN)
f(XIN)/2
f(XIN)/4
Instruction clock
f(XIN)/32
f(XIN)/4
f(XIN)/8
f(XIN)/16
Oscillation dividing
instruction
No use
CCK used
CCK2 used
CCK4 used
Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.
Machine cycle
The machine cycle is the cycle required to execute the
instruction.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34286G2GP#U0 | 功能描述:MCU 1.8/3.6V 2KB ROM 20-LSSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:720/4500 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| M34286G2GP#WC | 制造商:Renesas Electronics Corporation 功能描述:4BIT MCU |
| M34286G2-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M3429 SL001 | 制造商:Alpha Wire Company 功能描述:CBL 15PR 24AWG SLT 1000' |
| M3429 SL002 | 制造商:Alpha Wire Company 功能描述:CBL 15PR 24AWG SLT 500' |
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