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Rev.1.00
Aug 06, 2008
page 23 of 64
REJ03B0251-0100
4286 Group
LIST OF PRECAUTIONS
Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
connect a bypass capacitor (approx. 0.01 F) between pins
VDD and VSS at the shortest distance,
equalize its wiring in width and length, and
use the thickest wire.
Port E2 is also used as VPP pin. Connect this pin to VSS
through the resistor about 5k which is assigned to E2/VPP
pin as close as possible at the shortest distance.
Register initial values 1
The initial value of the following registers are undefined after
system is released from reset. After system is released from
reset, set initial values.
Register D (3 bits)
Register E (8 bits)
Register initial values 2
The initial value of the following registers are undefined at RAM
backup. After system is returned from RAM back-up, set initial
values.
Register X (4 bits)
Register Y (4 bits)
Register D (3 bits)
Register E (8 bits)
Stack registers (SKS)
Stack registers (SKs) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used when executing a table reference
instruction. Accordingly, be careful not to over the stack. The
contnts of registers SKs are destroyed when 4 levels are
exceeded.
Notes on unused pins
Timer
Count source
Stop timer 1 or timer 2 counting to change its count source.
Reading the count value
Stop timer 1 or 2 counting and then execute the data read
instruction (TAB1, TAB2) to read its data.
Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
Timer 1 count operation
When the bit 5 of the watchdog timer (WDT) is selected as
the timer 1 count source, the error of maximum ± 64 s (at
the minimum instruction execution time : 2 s) is generated
from timer 1 start until timer 1 underflow. When
programming, be careful about this error.
Stop of timer 2
Avoid a timing when timer 2 underflows to stop timer 2.
Writing to reload register R2H
When writing data to reload register R2H while timer 2 is
operating, avoid a timing when timer underflows.
Timer 2 carrier wave output function
When to expand “H” interval of carrier wave is valid, set “1”
or more to reload register R2H.
Timer 1 and timer 2 carrier wave output function
Count starts from the rising edge in Fig. 29 after the first
falling edge of the count source, after timer 1 and timer 2
operations start ① in Fig. 29.
Time to first underflow ③ in Fig. 29 is different from time
among next underflow ④ in Fig. 29 by the timing to start the
timer and count source operations after count starts.
Pin
D0–D7
E0, E1
E2
G0–G3
CARR
Connection
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open.
Connect to VSS.
Open (Set the output latch to “1” ).
Open (Set the output latch to “0” ).
Connect to VDD.
Open.
Usage condition
Pull-down transistor OFF.
(Note when connecting to VSS and VDD)
Connect the unused pins to VSS and VDD at the shortest
distance and use the thick wire against noise.
Fig. 29 Count start time and count time when operation
starts (T1, T2)
32
1
032
103
→
Timer start
Count source
Timer value
Timer underflow signal
Program counter
Make sure that the program counter does not specify after the
last page of the built-in ROM.