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參數(shù)資料
| 型號： | M34286G2-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大小： | 516K |
| 代理商： | M34286G2-XXXGP |
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Rev.1.00
Aug 06, 2008
page 7 of 64
REJ03B0251-0100
4286 Group
Fig. 1 AMC instruction execution example
Fig. 2 RAR instruction execution example
Fig. 3 Registers A, B and register E
FUNCTION BLOCK OPERATIONS
CPU
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, and bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-
bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
Fig. 4 TABP p instruction execution example
(CY)
(M(DP))
(A)
Addition
ALU
<Carry>
<Result>
CY
A3 A2 A1 A0
A0
CY A3 A2 A1
<Rotation>
RAR instruction
<Set>
SC instruction
<Clear>
RC instruction
A3 A2 A1 A0
B3 B2 B1 B0
ER7ER6ER5ER4ER3ER2ER1ER0
A3 A2 A1 A0
B3 B2 B1 B0
TAB instruction
TEAB instruction
TABE instruction
TBA instruction
Register B
Register A
Register B
Register A
Register E
Specifying address
p3 p2 p1 p0
PCH
DR2 DR1 DR0 A3 A2 A1 A0
PCL
Immediate field
value p
The contents
of register D
The contents
of register A
ROM
8
40
TABP p instruction
Low-order 4 bits
Middle-order 4 bits
Most significant 1 bit
URS flag (1)
URSC instruction
Register A (4)
Register B (4)
Carry flag CY (1)
相關(guān)PDF資料 |
PDF描述 |
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| M34286G2GP | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
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| M34506M4-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| M34506M2-XXXFP | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
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