參數資料
型號: M34282M2-XXXGP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 1 MHz, MICROCONTROLLER, PDSO20
封裝: 0.225 INCH, 0.65 MM PITCH, PLASTIC, SSOP-20
文件頁數: 36/71頁
文件大?。?/td> 547K
代理商: M34282M2-XXXGP
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instrunction
code
D8
D0
Flag CY
2
16
Rev.1.33
Mar 18, 2004
page 39 of 67
4282 Group
TAB1 (Transfer data to Accumulator and register B from timer 1)
001010111
057
11
Grouping:
Timer operation
Description: Transfers the contents of timer 1 to regis-
ters A and B.
Operation:
(B)
← (T17–T14)
(A)
← (T13–T10)
TABE (Transfer data to Accumulator and register B from register E)
000101010
02A
11
Grouping:
Register to register transfer
Description: Transfers the contents of register E to reg-
isters A and B.
Operation:
(B)
← (ER7–ER4)
(A)
← (ER3–ER0)
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
01001p3
p2
p1
p0
09p
13
0/1
Grouping:
Arithmetic operation
Description:
Transfers bits 7 to 4 to register B and bits 3 to 0 to register
A when URS flag is cleared to “0.” These bits 7 to 0 are the
ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) speci-
fied by registers A and D in page p.
Transfers bit 8 of ROM pattern is transferred to flag CY when
URS flag is set to “1” (after the URSC instruction is executed).
(One of stack is used when the TABP p instruction is executed.)
Operation:
SK(SP))
← (PC) , (SP) ← (SP) + 1
(PCH)
← p, p = 0 to 7, (PCL) ← (DR2–DR0, A3–A0)
When URS = 0,
(B)
← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0
When URS = 1,
(CY)
← (ROM(PC))8
(B)
← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0
(SP)
← (SP) – 1, (PC) ← (SK(SP))
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
TAB2 (Transfer data to Accumulator and register B from timer 2)
001000000
040
11
Grouping:
Timer operation
Description: Transfers the contents of timer 2 to regis-
ters A and B.
Operation:
(B)
← (T27–T24)
(A)
← (T23–T20)
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