
12
12-23
Rev.1.0
When it matches the attribute of the
selected parity, PAR = 0 is added.
When sending
D7
D6
D5
D4
D3
D2
D1
D0
PAR SP
ST
Attribute of D7 + D6 ++ D0
When it does not match the attribute of the
selected parity, PAR = 1 is added.
LSB
MSB
When receiving
D7
D6
D5
D4
D3
D2
D1
D0
PAR SP
ST
LSB
MSB
If the result of D7 + D6 ++ D0 + PAR does not
match he attribute of the selected parity, a parity error is
assumed.
Note 1: The data format shown above is an example for 8-bit UART mode.
Note 2: The data bit number (Dn) above only indicates a sequence of data, and does not represent the bit number (Dn) in the
register.
D8
D7
D6
D5
D4
D3
D2
D1
PAR
SP
ST
D0
Note 1 Note 2
9-bit UART mode
D7
D6
D5
D4
D3
D2
D1
D0
PAR
SP
ST
Note 1 Note 2
8-bit UART mode
D6
D5
D4
D3
D2
D1
D0
PAR
SP
ST
Note 1 Note 2
7-bit UART mode
D7
D6
D5
D4
D3
D2
D1
Clock synchronized mode
D0
Note 1: The parity bit can be chosen to be or not to be included.
Note 2: The stop bit length can be selected between one bit or two bits.
Direction of transfer
ST:Start Bit
PAR: Parity Bit
:Equivalent to one frame
D: Data Bit
SP: Stop Bit
When the attribute (odd or even) represented by
the number of 1's in the data bits matches that of
the selected parity, the SIO adds a parity bit
which is 0 to the transmit data. When the attribute
represented by the number of 1's in the data bits
does not match that of the selected parity, the
SIO adds a parity bit which is 1 to the transmit
data.
The received data is checked for parity to see if
the number of 1's in the data and parity bits
matches the attribute (odd or even) of the parity
(parity check).
Figure 12.2.7 Data Format where Parity is Enabled
SERIAL I/O
12.2 Serial I/O Related Registers