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9.3.8 Address Space
The address space in which DMA transfers can be performed is 64 Kbytes (H'0080 0000 to H'0080
FFFF) of internal peripheral I/O or RAM for both source and destination. The source and
destination addresses on each channel are set using the DMA Source Address and DMA
Destination Address Registers.
9.3.9 Transfer Operation
(1) Dual-address transfer
Regardless of the transfer unit, a DMA transfer is performed with two bus cycles consisting of a
source read access and a destination write access. (The transfer data is temporarily stored in the
DMAC's internal temporary register before being transferred.)
(2) Bus protocol and bus timing
The bus interface is shared with the CPU. Therefore, the bus protocol and bus timing both are the
same as in peripheral module access from the CPU.
(3) Transfer rate
The maximum transfer rate is calculated using the equation below.
(4) Address count direction and address change
The directions in which the source and destination addresses are counted (address fixed or
address increment) are set for each channel by using the SADSL (source address direction
select) bit and DADSL (designation address direction select) bit.
When "Address increment" is selected, the address is incremented by 2 when the transfer
unit = 16 bits or by 1 when the transfer unit = 8 bits each time one DMA transfer is performed.
Table 9.3.11 Address Count Direction and Address Change
Address count direction
Transfer unit
Address change for one DMA transfer performed
Address fixed
8 bits
0
16 bits
0
Address increment
8 bits
+1
16 bits
+2
DMAC
9.3 Functional Description of DMAC
Maximum transfer rate [bytes/second] = 2 bytes x
1 / f (BCLK) x 3 cycles
1