
10
10-20
Rev.1.0
10.2.4 Output Flip-flop Control Unit
The output flip-flop control unit controls the flip-flop (F/F) provided for each timer output. There are
following output flip-flop control registers.
F/F Protect Register 0 (FFP0)
F/F Protect Register 1 (FFP1)
F/F Data Register 0 (FFD0)
F/F Data Register 1 (FFD1)
Table 10.2.1 below lists the timing at which a signal for the output flip-flop is generated by each
timer.
Table 10.2.1 Timing at Which Signal for Output Flip-flop is Generated by Each Timer
Timer
Mode
Timing at which signal for output flip-flop is generated
TMS
(16-bit measurement input)
No signal generating function
TML
(32-bit measurement input)
No signal generating function
TID
Fixed period count mode
No signal generating function
Event count mode
No signal generating function
Multiply-by-4 event count mode
No signal generating function
Up/down event count mode
No signal generating function
TOM
PWM output mode
When counter is enabled or underflows
Single-shot PWM output mode
When counter underflows
Single-shot output mode
When counter is enabled or underflows
Successive output mode
When counter is enabled or underflows
INPUT/OUTPUT TIMERS
10.2 Common Timer Unit