![](http://datasheet.mmic.net.cn/30000/M30260M3A-XXXGP-U5_datasheet_2358673/M30260M3A-XXXGP-U5_146.png)
13. Serial I/O
page 132
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UARTi transmit/receive mode register (i=0, 1)
Symbol
Address
After reset
U0MR, U1MR
03A016, 03A816
0016
b7
b6
b5
b4
b3
b2
b1
b0
Bit
name
Bit
symbol
RW
CKDIR
SMD1
SMD0
Serial I/O mode select bit
(Note 2)
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
(b7)
Parity enable bit
0 : Internal clock
1 : External clock (Note 1)
Stop bit length select bit
Odd/even parity select bit
Reserve bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set value other than the above
b2 b1 b0
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
Write to "0"
Function
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
RW
UART2 transmit/receive mode register
Symbol
Address
After reset
U2MR
037816
0016
b7
b6
b5
b4
b3
b2
b1
b0
Bit
name
Bit
symbol
RW
CKDIR
SMD1
SMD0
Serial I/O mode select bit
(Note 2)
SMD2
Internal/external clock
select bit
STPS
PRY
PRYE
IOPOL
Parity enable bit
0 : Internal clock
1 : External clock (Note 1)
Stop bit length select bit
Odd/even parity select bit
TxD, RxD I/O polarity
reverse bit
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
0 1 0 : I2C bus mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
b2 b1 b0
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : No reverse
1 : Reverse
Function
Note 1: Set the corresponding port direction bit for each CLK2 pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxD2 pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL2 and SDA2 pins to “0” (input mode).
RW
(Note 3)
Figure 13.1.5. U0MR to U2MR registers