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14. A/D Converter
page 184
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A/D control register 0 (Note 1)
Symbol
Address
After reset
ADCON0
03D616
00000XXX2
b7
b6
b5
b4
b3
b2
b1
b0
Analog Input Pin
Select Bit (Note 2, 3)
CH0
Bit symbol
Bit name
Function
CH1
CH2
A/D Operation Mode
Select Bit 0 (Note 3)
MD0
MD1
Trigger Select Bit
TRG
ADST
A/D Conversion Start
Flag
0 : A/D conversion disabled
1 : A/D conversion started
Frequency Select Bit 0
CKS0
RW
A/D control register 1 (Note 1)
Symbol
Address
After reset
ADCON1
03D716
0016
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
A/D Sweep Pin
Select Bit
SCAN0
SCAN1
MD2
BITS
8/10-Bit Mode Select Bit
0 : 8-bit mode
1 : 10-bit mode
VCUT
VREF connect bit (Note 2)
A/D Operation Mode
Select Bit 1
1 : VREF connected
0
0 1 : Repeat mode
b4 b3
1
Frequency Select Bit 1
CKS1
0 : Any mode other than repeat sweep
mode 1
RW
Refer to Table 14.2 A/D Conversion
Frequency Select
Refer to Table 14.2 A/D Conversion
Frequency Select
(b7-b6)
1
Note 1: If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 2 (Note 1)
Symbol
Address
After reset
ADCON2
03D416
0016
b7
b6
b5
b4
b3
b2
b1
b0
A/D Conversion Method
Select Bit
Bit symbol
Bit name
Function
RW
SMP
Reserved Bit
Set to
“0”
0
A/D Input Group Select
Bit
0 0 : Select port P10 group (ANi)
0 1 : Select port P9 group (AN3i)
1 0 : Do not set
1 1 : Select port P9 group (AN24)
b2 b1
Frequency Select Bit 2
CKS2
ADGSEL0
ADGSEL1
RW
(b3)
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7-b6)
See Table 14.2 A/D Conversion
Frequency Select
RW
TRG1
Trigger Select Bit 1
b2 b1 b0
0 0 0 : Select AN0
0 0 1 : Select AN1
0 1 0 : Select AN2
0 1 1 : Select AN3
1 0 0 : Select AN4
1 0 1 : Select AN5
1 1 0 : Select AN6
1 1 1 : Select AN7
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: AN30 to AN32 and AN24 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in
the ADCON2 register to select the desired pin.
Note 3: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.
0 : Software trigger
1 : Hardware trigger (ADTRG trigger)
Invalid in repeat mode
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 s or more before
starting A/D conversion.
0 : Without sample and hold
1 : With sample and hold
Set to "0" in repeat mode
0
Figure 14.1.2.2 ADCON0 to ADCON2 Registers in Repeat Mode