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13. Serial I/O
page 136
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UART2 special mode register 3
Symbol
Address
After reset
U2SMR3
037516
000X0X0X2
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
Function
DL2
SDA digital delay
setup bit
(Note 1, Note 2)
DL0
DL1
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
b7 b6 b5
0 : Without clock delay
1 : With clock delay
Clock phase set bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
Clock output select bit
CKPH
NODC
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDA2 output by digital means during I2C bus mode. In other than
I2C bus mode, set these bits to “0002” (no delay).
Note 2 : The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
RW
(b0)
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
(b2)
(b4)
Figure 13.1.9. U2SMR3 register and U2SMR4 register
UART2 special mode register 4
Symbol
Address
After reset
U2SMR4
037416
0016
b7
b6 b5
b4
b3
b2
b1
b0
Bit name
Bit
symbol
RW
Function
ACKC
SCLHI
SWC9
Start condition
generate bit (Note)
Stop condition
generate bit (Note)
0 : Clear
1 : Start
SCL,SDA output
select bit
ACK data bit
Restart condition
generate bit (Note)
0 : Clear
1 : Start
0 : Clear
1 : Start
STAREQ
RSTAREQ
STPREQ
ACKD
0 : Start and stop conditions not output
1 : Start and stop conditions output
SCL output stop
enable bit
ACK data output
enable bit
0 : Disabled
1 : Enabled
0 : ACK
1 : NACK
0 : Serial I/O data output
1 : ACK data output
Note: Set to “0” when each condition is generated.
STSPSEL
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
SCL wait bit 3
RW