![](http://datasheet.mmic.net.cn/30000/M30240MC-XXXFP_datasheet_2358667/M30240MC-XXXFP_54.png)
CONFIDENTIAL
56
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
INXCSR5 (TX_FIFO_NOT_EMPTY):
The USB FCU sets this bit to a “1” when there is data in the IN FIFO. This bit in conjunction with IN_PKT_RDY
bit provides the transmit FIFO status information (see “IN (Transmit) FIFO” operation for details).
INXCSR6 (FLUSH):
The CPU writes a “1” to this bit to flush the IN FIFO. If there is one packet in the IN FIFO, a flush causes the
IN FIFO to be empty, if there are two packets in the IN FIFO, a flush causes the older packet to be flushed out
from the IN FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredictable results.
INXCSR7 (AUTO_SET):
If the CPU sets this bit to a “1”, the IN_PKT_RDY bit is set automatically by the USB FCU after the number
of bytes of data equal to the maximum packet size (MAXP) is written into the IN FIFO (see “IN (Transmit)
FIFO” operation for details).
Figure 47:
USB Endpoint x IN CSR
The USB Endpoint x OUT CSR (Control & Status Register), shown in Figure 48, contains control and
status information of the respective OUT endpoint 1-4.
OUTXCSR0 (OUT_PKT_RDY):
The USB FCU sets the this bit to a “1” after it successfully receives a packet of data from the host. This bit is
cleared by the CPU or by the USB FCU after a packet of data is unloaded from the FIFO (see “OUT (Receive)
FIFO” operation for details).
OUTXCSR1 (OVER_RUN):
This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun has occurred. The USB FCU sets
this bit to a “1” at the beginning of an OUT token if the OUTXCSR0 (OUT_PKT_RDY) bit is not cleared. Setting
this bit causes the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear this bit.
OUTXCSR2 (SEND_STALL):
The CPU writes a “1” to this bit when the endpoint is stalled (receiver halt). The USB FCU returns a STALL
handshake while this bit is set. The CPU writes a “0” to clear this bit.
OUTXCSR3 (ISO):
The CPU sets this bit to a “1” to initialize the respective endpoint as an Isochronous endpoint for OUT trans-
actions.
INXCSR0
IN_PKT_RDY Bit (bit 0) (Write “1” only or Read)
0: In packet is not ready
1: In packet is ready
INXCSR1
UNDER_RUN Flag (bit 1) (Write “0” only or Read)
0: No FIFO underrun
1: FIFO underrun has occurred
INXCSR2
SEND_STALL Bit (bit 2)
0: No action
1: Stall IN Endpoint X by the CPU
INXCSR3
ISO Bit (bit 3)
0: Select non-isochronous transfer
1: Select isochronous transfer
INXCSR4
INTPT Bit (bit 4)
0: Select non-rate feedback interrupt transfer
1: Select rate feedback interrupt transfer
INXCSR5
TX_NOT_EPT Flag (bit 5) (Read Only - Write “0”)
0: Transmit FIFO is empty
1: Transmit FIFO is not empty
INXCSR6
FLUSH Bit (bit 6) (Write Only - Read “0”)
0: No action
1: Flush the FIFO
INXCSR7
AUTO_SET Bit (bit 7)
0: AUTO_SET disabled
1: AUTO_SET enabled
MSB
7
LSB
0
INXCSR7 INXCSR6 INXCSR5 INXCSR4 INXCSR3
INXCSR1 INXCSR0
INXCSR2
Address: 031916
Access: R/W
Reset:
0016
Address: 032116
Address: 032916
Address: 033116