參數(shù)資料
型號: M30240M1-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝: 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 67/125頁
文件大?。?/td> 753K
代理商: M30240M1-XXXFP
CONFIDENTIAL
48
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
Universal Serial Bus
MAXP <= half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a “1” after it has success-
fully received a packet of data from the host. The CPU writes a “0” to the OUT_PKT_RDY bit after the packet
of data is unloaded from the OUT FIFO by the CPU/DMAC. In this configuration, the FIFO can store up to two
data packets at the same time, for back-to-back reception. Therefore, the OUT_PKT_RDY bit may remain set
after the CPU writes a “0” to it if there is another packet in the OUT FIFO.
Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of OUT CSR) = “1”:
MAXP > half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a “1” after it has successfully
received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a ‘0’ automatically
when the number of bytes of data equal to the MAXP (maximum packet size) is unloaded from the OUT FIFO
by the CPU/DMAC.
MAXP <= half of the OUT FIFO size: The USB FCU sets the OUT_PKT_RDY bit to a “1” after it has success-
fully received a packet of data from the host. The USB FCU clears the OUT_PKT_RDY bit to a “0” automati-
cally when the number of bytes of data equal to the MAXP (maximum packet size) is unloaded from the OUT
FIFO by the CPU/DMAC. In this configuration, the FIFO can hold up to two data packets at the same time, for
back-to-back reception. Therefore, the OUT_PKT_RDY bit may remain set after one packet (size equal to
MAXP) of data is unloaded if there is another packet in the OUT FIFO.
A software flush acts as if a packet is being unloaded from the OUT FIFO. If there is one packet in the OUT
FIFO, a flush causes the OUT FIFO to be empty, if there are two packets in the OUT FIFO, a flush causes the
older packet to be flushed out from the OUT FIFO.
USB Special Function Registers
The MCU controls USB operation through the use of special function registers (SFR). This section de-
scribes in detail each USB related SFR. Some USB special function registers have a mix of read/write,
read only, and write only register bits. Additionally, the bits may be configured to allow the user to write
only a “0” or a “1” to individual bits. When accessing these registers, writing a “0” to a register that can
only be set to a “1” by the CPU has no effect on that register bit. Each figure and description of the
special function registers details this operation.
USB attach / detach register
The USB attach / detach register is shown in Figure 30. The register is used to detach the USB func-
tion from a USB host without physically disconnecting the USB cable. The register is enabled in this
special mode by setting PORT83_SECOND high, this forces Port 8_3 to operate as a pull-up for D+(it
tri-states the port output driver and forces a “1” if Port 8_3 is read).When the attach/detach bit is high,
an attach is detected by the host; when set low, a detach is registered by the host. A 1.5K ohm pull-
up resistor must be added externally from port 83 to D+ to enable this mode. This mode is bypassed
when EXTCAP is used to pull up D+ via a 1.5 K ohm resistor.
Figure 30:
USB attach / detach register
PORT83_SECOND:
0 Normal mode for Port 8_3
1 Forces Port 8_3 to operate as pull-up for D+ enable special register.
ATTACH / DETACH (enabled when bit 0 is set to 1):
0 Will cause the host to eventually detect a detach.
1 Will cause host to detect attach.
Bit 7:2 Reserved
MSB
7
LSB
0
Address: 001F16
Access: R/W
Reset:
0016
Attach
P83_2nd
Reserved
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