參數(shù)資料
型號： M30240M1-XXXFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 103/125頁
文件大?。?/td> 753K
代理商： M30240M1-XXXFP
Mitsubishi microcomputers
M16C / 24 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
81
CONFIDENTIAL
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 75 and Figure 76 show the block diagram of the transmit/receive unit.
Figure 75:
Block diagram of UAR2 (i=0,1) transmit/receive circuit
Figure 76:
Block diagram of UART2 transmit/receive circuit
SP
PAR
2SP
1SP
UART
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock synchronous
type
TxDi
UARTi transmit register
PAR
enabled
PAR
disabled
D8
D7
D6
D5
D4
D3
D2
D1
D0
SP: Stop bit
PAR: Parity bit
UARTi transmit
buffer register
MSB/LSB conversion circuit
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UARTi receive
buffer register
UARTi receive register
2SP
1SP
PAR
enabled
PAR
disabled
UART
UART (7 bits)
UART (9 bits)
Clock
synchronous
type
Clock
synchronous type
UART (7 bits)
UART (8 bits)
RxDi
Clock
synchronous type
UART (8 bits)
UART (9 bits)
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
Data bus low-order bits
MSB/LSB conversion circuit
D7
D6
D5
D4
D3
D2
D1
D0
D8
000
0
00
SP
PAR
“0”
Data bus high-order bits
SP
PAR
2SP
1SP
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous
type
Clock
synchronous type
Data bus low-order bits
TxD2
UART2 transmit register
PAR
disabled
PAR
enabled
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 transmit
buffer register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
UART2 receive
buffer register
UART2 receive register
2SP
1SP
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART
(9 bits)
Clock
synchronous type
Clock
synchronous type
RxD2
UART
(8 bits)
UART
(9 bits)
Address 037E16
Address 037F16
Address 037A16
Address 037B16
Data bus high-order bits
D7
D6
D5
D4
D3
D2
D1
D0
D8
000
0000
SP
PAR
“0”
Reverse
No reverse
Error signal
output circuit
RxD data
reverse circuit
Error signal output
enable
Error signal output
disable
Reverse
No reverse
Logic reverse circuit + MSB/LSB conversion circuit
PAR
enabled
PAR
disabled
UART
Clock
synchronous
type
TxD data
reverse circuit
SP: Stop bit
PAR: Parity bit
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