參數(shù)資料
型號: M2V64S2DTP-7
廠商: Mitsubishi Electric Corporation
英文描述: 64M Synchronous DRAM
中文描述: 6400同步DRAM
文件頁數(shù): 33/51頁
文件大?。?/td> 430K
代理商: M2V64S2DTP-7
Feb.'00
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.3.2)
64M Synchronous DRAM
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
33
AC TIMING REQUIREMENTS
(Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level:
1.4V
AC timing is referenced to the
input signal crossing through
1.4V.
CLK
Signal
1.4V
1.4V
Symbol
Parameter
Limits
Unit
-7
-8
Min.
Max.
Min.
Max.
tCLK
CLK cycle time
CL=2
10
13
ns
CL=3
10
10
ns
tCH
CLK High pulse width
3
3
ns
tCL
CLK Low pulse width
3
3
ns
tT
Transition time of CLK
1
10
1
10
ns
tIS
Input Setup time
(all inputs)
2
2
ns
tIH
Input Hold time
(all inputs)
1
1
ns
tRC
Row Cycle time
70
70
ns
tRCD
Row to Column Delay
20
20
ns
tRAS
Row Active time
50
100K
50
100K
ns
tRP
Row Precharge time
20
20
ns
tWR
Write Recovery time
12
12
ns
tRRD
Act to Act delay
20
20
ns
tRSC
Mode Register Set Cycle time
10
10
ns
tREF
Refresh Interval time
64
64
ms
Min.
Max.
10
2.5
1
10
1.5
0.8
67.5
20
45
100K
20
12
15
10
64
-6
7.5
2.5
tRFC
Refresh Cycle time
80
80
ns
75
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