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參數(shù)資料
| 型號： | M1026-1Z-168.0400 |
| 英文描述： | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| 中文描述： | 才能開發(fā)出復雜基于時鐘鎖相環(huán)AUTOSWITCH |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 322K |
| 代理商： | M1026-1Z-168.0400 |
M1025/26 Datasheet Rev 1.0
9
of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
External Loop Filter
To provide stable PLL operation, the M1025/26 requires
the use of an external loop filter. This is provided via the
provided filter pins (see Figure 5).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
R
LOOP
C
LOOP
Figure 5: External Loop Filter
See Table 7, Example External Loop Filter Component
Values, below.
PLL Bandwidth is affected by loop filter component
values, the “M” value, and the “PLL Loop Constants”
listed in AC Characteristics on pg. 12.
The
MR_SEL3:0
settings can be used to actively change
PLL loop bandwidth in a given application. See “M and
R Divider Look-Up Tables (LUT)” on pg. 3.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
C
LOOP
OP_IN
nOP_IN
6
7
5
4
9
8
Example External Loop Filter Component Values
1
for M1025-yz-155.5200 and
M1026-yz-155.5200
VCSO Parameters: K
VCO
= 200kHz/V, R
IN
= 100k
(pin NBW = 0), VCSO Bandwidth = 700kHz.
Device Configuration
F
REF
(MHz)
(MHz)
19.44
2
155.52
0 0 0 0
8
38.88
3
155.52
0 0 0 1
16
77.76
4
155.52
0 1 0 1
8
77.76
5
155.52
0 1 1 0
32
155.52
4
155.52
1 0 1 0
16
155.52
5
155.52
1 0 1 1
64
Example External Loop Filter Comp. Values
R
LOOP
C
LOOP
Nominal Performance Using These Values
PLL Loop
Bandwidth
Factor
315
Hz
270
Hz
315
Hz
250
Hz
270
Hz
266
Hz
Table 7: Example External Loop Filter Component Values
F
VCSO
MR_SEL3:0 MDiv NBW
R
POST
C
POST
Damping
Passband
Peaking
(dB)
0.068
0.044
0.068
0.05
0.044
0.05
0
0
0
0
0
0
6.8
k
12
k
6.8
k
22
k
12
k
47
k
10
μ
F
10
μ
F
10
μ
F
4.7
μ
F
10
μ
F
2.2
μ
F
82
k
82k
82k
82k
82k
82k
1000
pF
1000
pF
1000
pF
1000
pF
1000
pF
1000
pF
5.4
6.7
5.4
6.0
6.7
6.2
Note 1: K
, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: This row is for the M1025 only.
Note 3: This row is for the M1026 only.
Note 4: Optimal for system clock filtering.
Note 5: Optimal for loop timing mode (LOL, AutoSwitch, or Hitless Switching should not be used).
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