- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358968 > M1026-1Z-168.0400 VCSO BASED CLOCK PLL WITH AUTOSWITCH PDF資料下載
參數(shù)資料
| 型號： | M1026-1Z-168.0400 |
| 英文描述： | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| 中文描述： | 才能開發(fā)出復(fù)雜基于時鐘鎖相環(huán)AUTOSWITCH |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 322K |
| 代理商： | M1026-1Z-168.0400 |
M1025/26 Datasheet Rev 1.0
5
of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
Implementation of single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50k
to Vcc and 50k
to ground. Figure 4 shows
the input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the
127
and
82
resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the
50
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (
nDIF_REF0
or
nDEF_REF1
) is left floating (not
connected), the input will self-bias at VCC/2.
PLL Operation
The M1025/26 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
frequency-lock the VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
Fvcso
Fin
×
=
For the available M divider and R divider look-up table
combinations,
Tables
3
and
4 on pg. 3
list the Total PLL
Ratio as well as Fin when using the
M1025-11-155.5200
or
the
M1026-11-155.5200
.
(“Ordering Information”, pg. 14
.
)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Post-PLL Divider
The M1025/26 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The
P_SEL
pin selects the value for the P divider: logic
1
sets P to
2,
logic
0
sets P to
1
. (See
Table 5 on
pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
MUX
0
REF_SEL
1
VCC
50k
50k
VCC
50k
50k
LVCMOS/
LVPECL
50k
50k
VCC
82
127
VCC
82
127
M1025/26
X
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
M
R
---
Fout
Fvcso
=
Fin
-----------------
×
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M14C04 | Memory Card IC 16/4 Kbit Serial IC Bus EEPROM |
| M14C04DD | M14C04 Die Description |
| M14C32 | Memory Micromodules General Information for D1, D2 and C Packaging |
| M14C32DD | TERMINAL BLOCK, 8WAY; Connector type:Terminal Block, Barrier; Material, contact:Copper alloy; Plating, contact:Bright Tin; Positions, No. of:8; Pitch:0.375"; Mounting type:PC Board; Wire size, AWG:12AWG; Approval Bodies:UL, CSA; RoHS Compliant: Yes |
| M14C64 | Memory Card IC 64/32 Kbit Serial IC Bus EEPROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1026-1Z-172.6423 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| M1026-1Z-173.3708 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| M10264-A1 | 功能描述:GPS模塊 GPS RF Ant Mod SiRF starIII Planar Mount RoHS:否 制造商:Linx Technologies 頻帶:1.575 GHz 通道數(shù)量:20 首次定位時間（冷啟動）:35 s 獲取敏感性:- 144 dBm 水平位置精確度:10 m 工作電源電壓:3 V to 4.2 V 工作電源電流:46 mA 接口類型:Serial 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 尺寸:15 mm x 13 mm x 2.2 mm |
| M10264-K1 | 功能描述:GPS開發(fā)工具 Evaluation Kit for M10214-A1 2 Modules RoHS:否 制造商:STMicroelectronics 產(chǎn)品:Evaluation Boards 工具用于評估:IT600, STM32F20x 頻率:1.575 GHz 工作電源電壓:1.8 V 接口類型:Wireless |
| M1026KS-6C-MMR | 制造商:MISCELLANEOUS 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。