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參數(shù)資料
| 型號(hào)： | M1026-1Z-168.0400 |
| 英文描述： | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| 中文描述： | 才能開發(fā)出復(fù)雜基于時(shí)鐘鎖相環(huán)AUTOSWITCH |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 322K |
| 代理商： | M1026-1Z-168.0400 |
M1025/26 Datasheet Rev 1.0
4
of 14
Revised 28Jul2004
Integrated Circuit Systems, Inc.
●
Networking & Communications
●
www.icst.com
●
tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P r o d u c t D a t a S h e e t
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
. The LOL pin should
not be used during loop timing mode.
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be
5MHz
or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive.
The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses
the
LOL
output for clock fault detection.
P Divider Look-Up Table (LUT)
The
P_SEL1
and
P_SEL0
pins select the post-PLL divider
value P. The output frequency of the SAW can be
divided by
1
or
2
or the output can be TriStated as
specified in
Table 5.
F
UNCTIONAL
D
ESCRIPTION
The M1025/26 is a PLL (Phase Locked Loop) based
clock generator that generates an output clock synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in
Tables
3
and
4 on pg. 3
. These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1025/26 includes a Loss of Lock (
LOL
) indicator,
which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1025/26. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails. Reference selection is
non-revertive, meaning that only one reference
reselection will be made each time that AutoSwitch is
re-enabled.
In addition to the AutoSwitch feature, Hitless Switching
and Phase Build-out options can be ordered with the
device. The Hitless Switching and Phase Build-out
options help assure SONET/SDH MTIE and TDEV
compliance during either a manual or automatic input
reference reselection.
P_SEL1:0
P Value
M1025-155.5200 or M1026-155.5200
Output Frequency (MHz)
0 0
2
0 1
1
1 0
2
1 1 TriState
Table 5: P Divider Look-Up Table (LUT)
77.76
155.52
77.76
N/A
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