參數(shù)資料
型號(hào)： LXP710PE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 34/84頁(yè)
文件大?。?/td> 1108K
代理商： LXP710PE
LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
34
Datasheet
Frame Pulse Sync & PLL Control Register
Address: 15
Abbreviation: FMSYNC_PLLCTL
Read/Write
Table 22. QRSS Test Pattern Control Register
Bit
Name
Default
Description
7, 6
n/a
0
Not used; Always read Low.
5
PATEN3
0
Loop 3 Test Pattern Generation/Detection Enable. When High, the internal
pattern is inserted into the mux HDSL payload. When Low, the incoming
mux E1 is inserted.
4
PATEN2
0
Loop 2 Test Pattern Generation/Detection Enable. When High, the internal
pattern is inserted into the mux HDSL payload. When Low, the incoming
mux E1 is inserted.
3
PATEN1
0
Loop 1 Test Pattern Generation/Detection Enable. When High, the internal
pattern is inserted into the mux HDSL payload. When Low, the incoming
mux E1 is inserted.
2
PATERRI3
0
Loop 3 Test Pattern Error Injection. When High, one bit error is injected into
loop payload. When Low, error injection is disabled. After two frame pulses
occurs, this bit is cleared.
1
PATERRI2
0
Loop 2 Test Pattern Error Injection. When High, one bit error is injected into
loop payload. When Low, error injection is disabled. After two frame pulses
occurs, this bit is cleared.
0
PATERRI1
0
Loop 1 Test Pattern Error Injection. When High, one bit error is injected into
loop payload. When Low, error injection is disabled. After two frame pulses
occurs, this bit is cleared.
Table 23. Frame Pulse Sync & PLL Control Register
Bit
Name
Default
Description
<7:5>
n/a
0
Not used; Always read Low.
4
SYNCEN
1
Loops Alignment Enable. When High, this bit enables synchronization of the
HDSL frames.
3
SYNCFM[1]
0
Frame Pulse Synchronization Select:
00: No frame synchronization
01: Sync with Loop 1 frame pulse
10: Sync with Loop 2 frame pulse
11: Sync with Loop 3 frame pulse
2
SYNCFM[0]
1
1
E1CLKSRC
0
E1 Clock Source Select; 1 = External Timing Source; 0 = Internal Timing
Source.
0
LOCKSEL
0
PLL Locking Time Select; 1 = Slow locking time; 0 = Fast locking time.
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