參數(shù)資料
型號: LXP710PE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 33/84頁
文件大小: 1108K
代理商: LXP710PE
HDSL Framer/Mapper for 1168 kbps Applications
LXP710
Datasheet
33
Address: 11
Abbreviation: L3TSCTL3
Read/Write
Address: 12
Abbreviation: L3TSCTL4
Read/Write
Programmable Idle Code Byte
Address: 13
Abbreviation: IDLECODE
Read/Write
QRSS Test Pattern Control
Address: 14
Abbreviation: PATCTL
Read/Write
Table 18. Loop 3 Time Slot Control Byte 2
Bit
Name
Default
Description
<7:0>
TSG<8:15>
0
Loop 3 Time Slot Grouping (Byte 2). Each bit that is set Low blocks transmission
of the corresponding DS0 channel in the mux E1 by forcing its bits to idle code.
Table 19. Loop 3 Time Slot Control Byte 3
Bit
Name
Default
Description
<7:0>
TSG<16:23>
0
Loop 3 Time Slot Grouping (Byte 3). Each bit that is set Low blocks transmission
of the corresponding DS0 channel in the mux E1 by forcing its bits to idle code.
Table 20. Loop 3 Time Slot Control Byte 4
Bit
Name
Default
Description
<7:0>
TSG<24:31>
0
Loop 3 Time Slot Grouping (Byte 4). Each bit that is set Low blocks transmission
of the corresponding DS0 channel in the mux E1 by forcing its bits to idle code.
Table 21. Programmable Idle Code Bytes
Bit
Name
Default
Description
<7:0>
IDLE<7:0>
FFh
Programmable Idle Code. This 8 bit code contains the byte used for channel
blocking. IDLE7 is the MSB and the first bit of E1 channel shifted out.
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