參數(shù)資料
型號： LXP710PE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 24/84頁
文件大?。?/td> 1108K
代理商： LXP710PE
LXP710
—
HDSL Framer/Mapper for 1168 kbps Applications
24
Datasheet
Mux E1 Control Register
Address: 00
Abbreviation: MXE1CTL
Read/Write
75
117
DXL3EOCL
R
Demux loop 3 EOC message (Low byte)
76
118
DXL3UIB
R
Demux loop 3 UIB bits
77
119
DXL3CRCEC
R
Demux loop 3 CRC error count
78
120
DXL3FEBEEC
R
Demux loop 3 FEBE error count
79
121
DXL3BPVEC
R
Demux loop 3 BPV error count
7A
122
L3PATECH
R
Loop 3 QRSS test pattern error counter (High byte)
7B
123
L3PATECL
R
Loop 3 QRSS test pattern error counter (Low byte)
7C
124
MX3RSCNTR
R
Loop 3 mux restart counter
7D
125
VER
R
HFMA version number
7E
126
MXTEST
R/W
μ
P mode testing register for mux
7F
127
DXTEST
R/W
μ
P mode testing register for demux
Table 2. Register Summary (Continued)
Hex
Address
Decimal
Address
Symbol
Type
Description
Table 3. Mux E1 Control Register
Bit
Name
Default
Description
7
n/a
0
Not used; Always read Low.
6
n/a
0
Not used; Always read Low.
5
INVMXCK
0
Invert Mux E1 Input Clock. When High, the rising edge of E1CLKI samples the mux
E1 data and frame mark. When this bit is Low, the falling edge samples the data
and frame mark.
4
NMCKEN
0
Nominal Clock Enable. When High, nominal clock is selected to input the
MX_PROCESS block. When Low, E1 recovered clock is selected to input the
MX_PROCESS block.
3
NMFMEN
0
Nominal Frame Pulse Enable. When High, nominal frame pulse is selected to input
the MX_PROCESS block. When Low, Demux E1 frame pulse is selected to input
the MX_PROCESS block.
2
MXSLIDEN
1
MUx Sliding Enable. When High, sliding mode is selected. When Low, jerking mode
is selected.
1
SNDMXAIS
0
Send Mux E1 AIS. When High, E1 AIS is inserted into the mux HDSL payload of
two/three loops. When Low, the incoming E1 is inserted. This control bit is ORed
with the FRCMAIS input pin (when enabled) to control mux AIS.
0
EXTMAIS
0
External Mux AIS Enable. When High, the FRCMAIS input pin is enabled to insert
mux E1 AIS. When Low, mux AIS insert is controlled solely by the SNDMAIS
control bit.
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