LV25450PNW
No.A1668-8/40
Test data pattern
PLL IN1 data
CCB address
Control data 1
Control data 2
Control data 3
Control data 4
IN1
Data contents
A0
A1
A2
A3
A4
A5
A6
A7
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
OS
C_D1
OS
C_D2
AM/F
M
DVS
R0
R1
R2
R3
OSC_DI
V
WB
DE
L
A
Y
_ADJ
0
DE
L
A
Y
_ADJ
1
DE
L
A
Y
_ADJ
2
--
-
FM
FIL
AMF
IL
PLL
Counter
value
D
elay
-A
dj
15 FM_US98.1M fref = 100kHz
0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0
2176
0
22 FM_JP83M fref = 100kHz,
Delay = 1
0 0 0 1 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0
2169
1
33 MW1000k fref = 10k (USA)
0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1
23400
0
PLL IN2 data
CCB address
Control data 1
Control data 2
Control data 3
Control data 4
IN2
Data contents
A0
A1
A2
A3
A4
A5
A6
A7
--
-
--
-
--
-
--
-
--
-
X_S
W
_
0
X_S
W
_
1
X_S
W
_
2
XLV
L0
XLV
L1
XLV
L2
A
LC_
OFF
--
-
--
-
--
-
--
-
--
-
--
-
O
F
SET
_
SW
--
-
ULD
UL0
UL1
TW
O_
DOFF
--
-
--
-
DZ0
DZ1
DLC
TE
S
T0
TE
S
T1
TE
S
T2
X'
tal-
Ad
j
X'tal-
Lev
el
13 FM reception mode settings
(Trm=OFF)
1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0
4
15 MW reception mode settings
1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0
4
21 FM reception mode settings
(Trm=ON)
1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0
4
PLL IN3-1 data
CCB address
Control data 1
Control data 2
Control data 3
Control data 4
IN3-
1
Data contents
A0
A1
A2
A3
A4
A5
A6
A7
RFDAC0
RFDAC1
RFDAC2
RFDAC3
RFDAC4
RFDAC5
RFDAC6
RFDAC7
RFDAC8
TUNEROFF
ANT
D
A
C
0
ANT
D
A
C
1
ANT
D
A
C
2
ANT
D
A
C
3
ANT
D
A
C
4
ANT
D
A
C
5
ANT
D
A
C
6
ANT
D
A
C
7
ANT
D
A
C
8
REG_A
D
J0
REG_A
D
J1
XS0
XS1
DAC9
_S
W2
DAC9
_S
W
IQ
MIX_G
A
IN
IQ
_S
W
FM
A
G
C_
ON
AM
AG
C_O
N
IFA
G
C_
OFF
DT
EST
SW
Sub-
Addr
es
s
RF-DAC
ANT-DAC
1 Bit-Check-0
1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0
2 Bit-Check-1
1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
1
3 Bit-Check-2
1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
2
5 Bit-Check-4
1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
4
6 Bit-Check-7
1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
7
7 Bit-Check-8
1 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
8
8 Bit-Check-15
1 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
15
9 Bit-Check-16
1 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
16
10 Bit-Check-31
1 0 0 1 0 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
31
11 Bit-Check-32
1 0 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
32
12 Bit-Check-63
1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
63
13 Bit-Check-64
1 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
64
14 Bit-Check-127
1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
127
15 Bit-Check-128
1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
128
16 Bit-Check-255
1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
255
17 Bit-Check-256
1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
256
18 Bit-Check-511
1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0
511
25 Standard FM (Upper)
1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0
256
26 Standard FM
1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0
27 Standard FM (Lower)
1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
256
30 Tuner-OFF(FM)
1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0
256
PLL IN3-2 data
CCB address
Control data 1
Control data 2
Control data 3
Control data 4
IN3-
2
Data contents
A0
A1
A2
A3
A4
A5
A6
A7
W_
AG
C0
W_
AG
C1
W_
AG
C2
W_
AG
C3
N_AGC0
N_AGC1
N_AGC2
N_AGC3
EV
A2
(
X
ta
l)
--
-
--
-
VREG
4
V
_O
F
KEY_A
G
C0/RFA
G
C
_H0
KEY_A
G
C1/RF
A
GC_H1
KEY_A
G
C2/RFA
G
C
_H2
KEY_A
G
C3/RFA
G
C
_H3
A
P
F_
A
DJ0
/RFA
G
C_
S
0
A
P
F_
A
DJ1
/RFA
G
C_
S
1
A
P
F_
A
DJ2
/RFA
G
C_
S
2
A
P
F_
A
DJ3
/RFA
G
C_
S
3
S_MET
E
R0
S_M
E
T
E
R1
S_M
E
T
E
R2
S_M
E
T
E
R3
S_M
E
T
E
R4
ADJ
_N0
ADJ
_N1
ADJ
_N2
--
-
FM
FE
TOFF
W_
KE
YED
Sub-
Addr
es
s
Wid
e-
AG
C
Narrow-AGC
Key
ed-
AG
C
A
M
-RFA
GC
Ha
rd
AM-
R
F
A
G
C
So
ft
FM
-S
-m
et
er
S
h
ift
er
IF
AG
C-
Am
pG
a
in
13 FM (W-AGC-Bit = 0)
1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1
0
7
0
7
15
3
15 FM (W-AGC-Bit = 15)
1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1
15 7
0
7
15
3
16 FM (N-AGC-Bit = 0)
1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1
7
0
7
15
3
18 FM (N-AGC-Bit = 15)
1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1
7 15 0
7
15
3
25 Standard FM-2
1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 0 1
7
0
7
15
3
25B Standard FM-2
Vsm-Shifter After the
adjusting
1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 0 *
*
1 1 0 0 0 0 1
7
0
7
7 Adjust-
ment
3
26 Standard AM-2
1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1
7
0
6 12
15
3
27 AM (W-AGC-Bit = 0)
1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1
0
7
0
6 12
15
3
29 AM (W-AGC-Bit = 13)
1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1
13 7
0
6 12
15
3
30 AM (N-AGC-Bit = 0)
1 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1
7
0
6 12
15
3
32 AM (A-AGC-Bit = 15)
1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1
7 15 0
6 12
15
3
58 Standard FM-2 Trm=ON
APF-Adj=10
1 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 0 1 1 0 0 0 0 1
7
1
7
5
15
3
Items marked with an asterisk are Vsm adjustment items. The bit values after adjustment must be retained.