LV25450PNW
Continued from preceding page.
No.
Control block/data
Description
Related data
(11)
Crystal oscillator oscillation
level
adjustment data
XLVL0 to XLVL2
Data used to adjust the crystal 4.5MHz oscillation level when the S/N condition is
worsening.
X’tal OSC oscillation level adjustment
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Low
↓
High
R0 to R3,
X_SW_0 to
X_SW_2
(12)
Crystal oscillator
ACL circuit
ON/OFF switching
ALC_OFF
Switches on and off the ALC (Auto level control) in the crystal oscillation circuit. Normally
set to high.
ALC_ON/OFF
switching
0
1
ALC_OFF
Normal operation (ALC_ON)
(13)
DO pin control data
ULD
Determines the DO pin output.
DO pin control data
ULD
DO pin
0
Low when not locked.
1
Open
* In such a case that the DO pin is multiplexed with EEPROM, transmit a setting data that
opens the LV25450PNW DO pin control just before reading out the EEPROM data.
The following item (14) must also be set when monitoring the unlock detection signal.
UL0, UL1
(14)
Unlock state detection data
UL0, UL1
Selects the phase error (E) detection width used to judge the PLL locked state.
If a phase error in excess of the E detection width from the table below occurs, the
PLL is seen as being in the unlocked state.
When the PLL is seen as being unlocked, the detection pin (DO) is set low.
UL1
UL0
φE detection width
Detection pin output
0
1
0
1
0
1
Stopped
0
±0.5
μs
±1
μs
Open
φE is output directly
φE is delayed by 1 to 2 ms.
ULD
≈
Delay
Unlock state output
1 to 2ms
DO
φE
≈
(15)
Crystal oscillator buffer
output stop switching
TWO_DOFF
Stops the crystal oscillator buffer output.
1 bit
Crystal oscillator
buffer switching
0
1
Normal operation
Stopped
(16)
Phase comparator control
data
DZ0, DZ1
Controls the phase comparator's dead zone.
DZ1
DZ0
Dead zone mode
0
1
0
1
0
1
DZA
DZB
DZC
DZD
The DZA setting is selected after the power-on reset.
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