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參數(shù)資料
| 型號： | LV25450PNW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 調(diào)諧器 |
| 英文描述： | AUDIO TUNER, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 28/40頁 |
| 文件大?。?/td> | 1251K |
| 代理商： | LV25450PNW |
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LV25450PNW
No.A1668-34/40
Continued from preceding page.
No.
Control block/data
Description
Related data
(17)
Charge pump control data
DLC
Forcibly sets the charge pump output to the low level (VSS level).
DLC = 1 : Low level
DLC = 0 : Normal operation
* : If the IC deadlocks with VCO oscillator stopped with the VCO control voltage (Vtune) at
0 V, the deadlock can be resolved by setting the charge pump output to the low level
and setting Vtune to VCC.
This item is set to the normal operation state after the power-on reset.
(18)
IC internal signal I/O port
control data
TEST0, TEST1, TEST2
Specifies the I/O direction for the I/O ports
Data = 0 : Input port. The value 0 should be specified in normal operation.
= 1 : Output port. A value of 1 is used for IC testing.
* : This data must be set to 0 at all times other than IC evaluation.
(19)
RF tuning D/A converter
output
RFDAC0 to RFDAC8
Applies a control voltage to the RF tuning circuit (varactor).
9 bit
DAC9_SW2,
DAC9_SW
(20)
Tuner off setting
TUNEROFF
Set the IC to tuner off mode.
1 bit
Tuner OFF mord
0
1
Normal operation
Tuner-OFF
(21)
Antenna tuning D/A
converter output
ANTDAC0 to ANTDAC8
Applies a control voltage to the antenna tuning circuit (varactor).
9 bit
DAC9_SW2,
DAC9_SW
(22)
2.7V REG
ADJ
REG_ADJ0
REG_ADJ1
Adjusts the 2.7 V regulator
2.7V REG ADJ
0 0
0 1
1 0
1 1
-23mV
(Center value)
+23mV
+64mV
(23)
RF block tuning circuit
temperature characteristics
compensatioin slope
switching
data
DAC9_SW2
DAC9_SW
RF block tuning circuit temperature characteristics compensatioin slope switching bits
9bit temperature characteristics compensatioin slope switching
0 0
0 1
1 0
1 1
Standard (Gradual)
RFDAC0 to
RFDAC8,
ANTDAC0 to
ANTDAC8
(24)
IQ mixer gain adjustment
data
IQMIX_GAIN
Data used to switch FM IQ mixer gain.
1 bit
IQ mixer gain adjustment
0
1
Gain Down (with RF-Amp)
Gain Up (without RF-Amp)
(25)
IQ mixer phase switching
data
IQ_SW
Data used to switch FM IQ mixer phase.
1 bit
IQ mixer phase switching
0
1
Lower
Upper
(26)
Forced AGC (AM/FM)
switching data
FMAGC_ON
AMAGC_ON
Data used to operate the forced AGC circuit (antenna dumping).
FMAGC_ON : FM AGC
0 = NORMAL, 1 = ON
AMAGC_ON : AM AGC
0 = NORMAL, 1 = ON
Each 1 bit
Continued on next page.
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