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參數(shù)資料
| 型號： | LTUX |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| 中文描述： | 1-/2-Channel 20位ADC的無延遲UPower采用MSOP - 10 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 375K |
| 代理商： | LTUX |
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16
LTC2421/LTC2422
24212f
APPLICATIOU
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
W
U
U
Figure 6. External Serial Clock, Single Cycle Operation
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
ANALOG INPUT RANGE
ZS
SET
– 0.12V
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
μ
F
1
10
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
V
CC
3-WIRE
SERIAL I/O
EOC
CH0/CH1
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
MSB
LSB
20
EXR
SIG
BIT 0
BIT 4
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
SLEEP
DATA OUTPUT
CONVERSION
24212 F06
CONVERSION
Hi-Z
Hi-Z
Hi-Z
TEST EOC
TEST EOC
CS HIGH anytime between the first rising edge and the
24th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 24 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
Figure 7. External Serial Clock, Reduced Data Output Length
V
CC
F
O
FS
SET
ZS
SET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZS
SET
+ 0.1V TO V
CC
ANALOG INPUT RANGE
ZS
SET
– 0.12V
TO
FS
SET
+ 0.12V
REF
(V
REF
= FS
SET
– ZS
SET
)
0V TO FS
SET
– 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
μ
F
1
10
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2422
V
CC
3-WIRE
SERIAL I/O
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
TEST EOC
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
24212 F07
MSB
EXR
SIG
BIT 8
BIT 19
BIT 9
BIT 20
BIT 21
BIT 22
EOC
CH0/CH1
BIT 23
BIT 0
EOC
Hi-Z
TEST EOC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTUY | 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| LTUZ | 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| LTVA | 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| LTC2450 | Easy-to-Use, Ultra-Tiny 16-Bit ADC |
| LTC2450-1 | Easy-to-Use, Ultra-Tiny 16-Bit ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTUY | 制造商:LINER 制造商全稱:Linear Technology 功能描述:1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
| LTUZ | 制造商:LINER 制造商全稱:Linear Technology 功能描述:1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 |
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