參數(shù)資料
型號(hào)： LTC6990IS6#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： XO, clock
英文描述： VCO, 0.000488 MHz - 2 MHz
封裝： LEAD FREE, PLASTIC, TSOT-23, 6 PIN
文件頁(yè)數(shù)： 5/28頁(yè)
文件大小： 310K
代理商： LTC6990IS6#TRPBF
LTC6990
13
6990f
OPERATION
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6990 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE =16 (ΔDIVCODE+ 6) tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital lter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
Start-Up Time
When power is rst applied to the LTC6990 the power-on
reset (POR) circuit will initiate the start-up time, tSTART.
The OUT pin is oated (high-impedance) during this time.
The typical value for tSTART ranges from 0.5ms to 8ms
depending on the master oscillator frequency (indepen-
dent of NDIV):
tSTART(TYP) = 500 tMASTER
The start-up time may be longer if the supply or DIV
pin voltages are not stable. For this reason, it is recom-
mended to minimize the capacitance on the DIV pin so it
will properly track V+.
Figure 5. DIVCODE Change from 5 to 2
Figure 6. Typical Start-Up
100μs/DIV
6990 F05
DIV
1V/DIV
OUT
1V/DIV
V+ = 3.3V
RSET = 200k
576μs
100μs/DIV
6990 F06
V+
1V/DIV
OUT
1V/DIV
V+ = 2.5V
DIVCODE = 4
RSET = 50k
OUTPUT CONNECTED
TO 1.25V THROUGH 25k
TO SHOW Hi-Z
470μs
相關(guān)PDF資料
PDF描述
LTP-537HR
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LTS-313AY
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LTS-4910AHR
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