參數(shù)資料
型號: LTC4270AIUKG#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC52
封裝: 8 X 7 MM, LEAD FREE, PLASTIC, QFN-52
文件頁數(shù): 15/32頁
文件大?。?/td> 344K
代理商: LTC4270AIUKG#TRPBF
LTC4270/LTC4271
22
42701fa
APPLICATIONS INFORMATION
Table 6. Example Current Limit Settings
ILIM (mA)
INTERNAL REGISTER SETTING (hex)
RSENSE = 0.5Ω
RSENSE = 0.25Ω
53
88
106
08
88
159
89
213
80
08
266
8A
319
09
89
372
8B
425
00
80
478
8E
531
92
8A
584
CB
638
10
90
744
D2
9A
850
40
C0
956
4A
CA
1063
50
D0
1169
5A
DA
1275
60
E0
1488
52
49
1700
40
1913
4A
2125
50
2338
5A
2550
60
2975
52
ILIM Foldback
The LTC4270/LTC4271 features a two-stage foldback circuit
that reduces the port current if the port voltage falls below
the normal operating voltage. This keeps MOSFET power
dissipation at safe levels for typical 802.3af MOSFETs,
even at extended 802.3at power levels. Current limit and
foldback behavior are programmable on a per-port basis.
Table 6 gives examples of recommended ILIM register
settings.
The LTC4270/LTC4271 will support current levels well
beyond the maximum values in the 802.3at specification.
The shaded areas in Table 6 indicate settings that may
require a larger external MOSFET, additional heat sinking,
or setting tLIM Enable.
MOSFET Fault Detection
LTC4270/LTC4271 PSE ports are designed to tolerate
significant levels of abuse, but in extreme cases it is pos-
sible for the external MOSFET to be damaged. A failed
MOSFET may short source to drain, which will make the
port appear to be on when it should be off; this condition
may also cause the sense resistor to fuse open, turning
off the port but causing the LTC4270 SENSE pin to rise
to an abnormally high voltage. A failed MOSFET may also
short from gate to drain, causing the LTC4270 GATE pin
to rise to an abnormally high voltage. The LTC4270 OUT,
SENSE and GATE pins are designed to tolerate up to 80V
faults without damage.
If the LTC4270/LTC4271 sees any of these conditions for
more than 180μs, it disables all port functionality, reduces
the gate drive pull-down current for the port and reports
a FET Bad fault. This is typically a permanent fault, but
the host can attempt to recover by resetting the port, or
by resetting the entire chip if a port reset fails to clear the
fault. If the MOSFET is in fact bad, the fault will quickly
return, and the port will disable itself again. The remaining
ports of the LTC4270/LTC4271 are unaffected.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a tSTART fault if the LTC4270/LTC4271
attempts to turn on the port.
Port Current Readback
The LTC4270/LTC4271 measures the current at each port
with an internal A/D converter. Port data is only valid when
the port power is on and reads zero at all other times. The
converter has two modes:
100ms mode: Samples are taken continuously and the
measured value is updated every 100ms
1s mode: Samples are taken continuously; a moving 1
second average is updated every 100ms
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