參數(shù)資料
型號: LTC4251IS6
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6
封裝: 1 MM HEIGHT, PLASTIC, MO-193, TSOT-23, 6 PIN
文件頁數(shù): 4/20頁
文件大小: 235K
代理商: LTC4251IS6
LTC4251/LTC4251-1/
LTC4251-2
12
425112fa
GATE
GATE is pulled low to VEE under any of the following
conditions: in UVLO, during the initial timing cycle, in an
overvoltage condition, or when the LTC4251/LTC4251-1/
LTC4251-2 are latched off after a short-circuit. When
GATE turns on, a 58
AcurrentsourcechargestheMOSFET
gate and any associated external capacitance. VIN limits
gate drive to no more than 14.5V.
Gate-drain capacitance (CGD) feed through at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN,
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating CGD. Instead, a smaller value (≥10nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to VEE. If SENSE
exceeds 50mV, the CB comparator activates the 230
A
TIMER pull-up. At 100mV, the ACL amplifier servos the
MOSFET current, and at 200mV the FCL comparator
abruptly pulls GATE low in an attempt to bring the MOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge CT to 4V (see Equa-
tion (2)), the LTC4251/LTC4251-1/LTC4251-2 latch off
and pull GATE low.
If the SENSE pin encounters a voltage greater than 100mV,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE over-
drives the MOSFET in normal operation, the ACL amplifier
needs time to discharge GATE to the threshold of the
MOSFET. For a mild overload, the ACL amplifier can
control the MOSFET current, but in the event of a severe
overload the current may overshoot. At SENSE = 200mV,
the FCL comparator takes over, quickly discharging the
GATE pin to near VEE potential. FCL then releases, and the
ACL amplifier takes over. All the while TIMER is running.
The effect of FCL is to add a nonlinear response to the
control loop in favor of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop, and GATE under-
shoots. A zero in the loop (resistor RC in series with the
gate capacitor) helps the ACL amplifier recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load-side low impedance
short is shown in Figure 4. Initially, the current overshoots
the analog current limit level of VSENSE = 100mV (Trace 2)
as the GATE pin works to bring VGS under control (Trace 3).
The overshoot glitches the backplane in the negative
direction, and when the current is reduced to 100mV/RS
the backplane responds by glitching in the positive
direction.
TIMER commences charging CT (Trace 4) while the analog
current limit loop maintains the fault current at 100mV/RS,
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. When CT reaches 4V,
GATE turns off, the load current drops to zero and the
backplane rings up to over 100V. The positive peak is
usually limited by avalanche breakdown in the MOSFET,
and can be further limited by adding a zener diode across
the input from – 48V to – 48RTN, such as Diodes Inc.
SMAT70A.
A low-impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 4, Trace 1, can
rob charge from output capacitors on adjacent cards. When
the faulty card shuts down, current flows in to refresh the
APPLICATIO S I FOR ATIO
WU
UU
FAULT DUTY CYCLE, D (%)
20
40
60
80
0
NORMALIZED
RESPONSE
TIME
(s/
F)
10
1
0.1
0.01
100
425112 F03
t
CT(F)
4
(235.8 D) – 5.8
=
Figure 3. Circuit Breaker Response Time
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