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參數(shù)資料
| 型號： | LTC1705 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual 550kHz Synchronous Switching Regulator Controller with 5-Bit VID and 150mA LDO |
| 中文描述： | 雙550kHz的同步開關(guān)，5位VID和150mA LDO穩(wěn)壓器控制器 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LTC1705 |
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LTC1705
14
APPLICATIU
W
U
U
MIN/MAX Comparators
Two additional feedback loops keep an eye on the main
feedback amplifier and step in if the feedback node moves
±
5% from its nominal 800mV value. The MAX comparator
(see Block Diagram) activates if FB rises more than 5%
above 800mV. It immediately turns the top MOSFET (QT)
off and the bottom MOSFET (QB) on and keeps them that
way until FB falls back within 5% of its nominal value. This
pulls the output down as fast as possible, preventing
damage to the (often expensive) load. If FB rises because
the output is shorted to a higher supply, QB will stay on
until the short goes away, the higher supply current limits
or QB dies trying to save the load. This behavior provides
maximum protection against overvoltage fault at the out-
put, while allowing the circuit to resume normal operation
when the fault is removed.
The MIN comparator (see Block Diagram) trips if FB is
more than 5% below 800mV and immediately forces the
switch duty cycle to 90% to bring the output voltage back
into range. It releases when FB is within the 5% window.
MIN is disabled when the soft-start or current limit circuits
are active—the only two times that the output should
legitimately be below its regulated value.
Notice that the FB pin is the virtual ground node of the
feedback amplifier. A typical compensation network does
not include local DC feedback around the amplifier, so that
the DC level at FB will be an accurate replica of the output
voltage, divided down by R1 and R
B
(Figure 3). However, the
compensation capacitors will tend to attenuate AC signals
at FB, especially with low bandwidth Type 1 feedback loops.
This can create a situation where the MIN, MAX and PGOOD
comparators do not respond immediately to shifts in the
output voltage, if they monitor the output at FB. With VID
code switching on the fly, this problem is aggravated.
To overcome this, a second resistor divider is used (see
Block Diagram) to provide the MIN, MAX and PGOOD
comparators with an accurate replica of the output voltage.
This ensures that the comparators react rapidly to code
changes. For the I/O channel, the output voltage is indepen-
dent of VID codes and therefore the change in V
OUT
is
minimized. Maximizing I/O feedback loop bandwidth will
minimize these delays and allow MIN and MAX to operate
properly. See the Feedback Loop/Compensation section.
PGOOD Flag
The LTC1705 incorporates a power good pin (PGOOD).
PGOOD is an open-drain output and requires an external
pull-up resistor. If all three regulators are typically within
±
10% of their nominal value, transistor MPG shuts off (see
Block Diagram) and PGOOD is pulled high by the external
pull-up resistor. If any of the three outputs is more than
10% outside the nominal value for more than 4
μ
s, PGOOD
pulls low, indicating that an output is out of regulation. For
PGOOD to pull high, all three outputs must be in regulation
for more than 20
μ
s. PGOOD remains active during soft
start and current limit. On power up, PGOOD pulls low. As
soon as the RUN/SS pin rises above the shutdown thresh-
old, the three pair of power good comparators take over
and control the transistor MPG directly. The 4
μ
s and 20
μ
s
delay ensure that short output transient glitches, that are
successfully “caught” by the power good comparators,
don’t cause momentary glitches at the PGOOD pin.
For the core channel, if there is a VID code change, the
internal DAC responds by switching its output voltage
immediately. However, the switching power supply output
slew rate is limited by the output filter. If the VID code step
change is small, the power good comparator might not
register any transition. To acknowledge the code transi-
tion command , the LTC1705 forces PGOOD to pull low for
20
μ
s once there is a VID code change. After this short
interval, the power good comparators decide the PGOOD
status.
Shutdown/Soft-Start
The RUN/SS pin performs two functions: if pulled to
ground, it shuts down the LTC1705 and it acts as a
conventional soft-start pin, enforcing a maximum duty
cycle limit proportional to the voltage at RUN/SS. An
internal 3
μ
A current source pull-up is connected to the
RUN/SS pin, allowing a soft-start ramp to be generated
with a single external capacitor to ground. The 3
μ
A current
source is active even if the LTC1705 is shut down, ensur-
ing the device will start when any external pull-down at
RUN/SS is released. In shutdown, the LTC1705 enters
micropower sleep mode and quiescent current drops
typically below 50
μ
A.
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