參數(shù)資料
型號(hào)： LTC1403CMSE-1#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Serial 12-Bit, 2.8Msps Sampling ADCs with Shutdown; Package: MSOP; No of Pins: 10; Temperature Range: 0°C to +70°C
中文描述： 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封裝： LEAD FREE, PLASTIC, MSOP-10
文件頁(yè)數(shù)： 7/22頁(yè)
文件大?。?/td> 575K
代理商： LTC1403CMSE-1#PBF
LTC1403-1/LTC1403A-1
14031fb
applications inFormation
OneormorerisingedgesatSCKwakeuptheLTC1403-1/
LTC1403A-1forserviceveryquickly,andCONVcanstart
anaccurateconversionwithinaclockcycle.Fourrising
edgesatCONV,withoutanyinterveningrisingedgesat
SCK,puttheLTC1403-1/LTC1403A-1inSleepmodeand
thepowerdraindropsfrom16mWto10W.Oneormore
risingedgesatSCKwakeuptheLTC1403-1/LTC1403A-1
foroperation.Theinternalreference(VREF)takes2msto
slewandsettlewitha10Fload.Notethat,usingsleep
modemorefrequentlythanevery2ms,compromisesthe
settledaccuracyoftheinternalreference.Notethat,for
slowerconversionrates,theNapandSleepmodescanbe
usedforsubstantialreductionsinpowerconsumption.
DIGITAL INTERFACE
TheLTC1403-1/LTC1403A-1hasa3-wireSPI(SerialPro-
tocolInterface)interface.TheSCKandCONVinputsand
SDOoutputimplementthisinterface.TheSCKandCONV
inputsacceptswingsfrom3VlogicandareTTLcompat-
ible,ifthelogicswingdoesnotexceedVDD.Adetailed
descriptionofthethreeserialportsignalsfollows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but
subsequent rising edges at CONV are ignored by the
LTC1403-1/LTC1403A-1untilthefollowing16SCKrising
edgeshaveoccurred.Itisnecessarytohaveaminimum
of16risingedgesoftheclockinputSCKbetweenris-
ingedgesofCONV.Buttoobtainmaximumconversion
speed,itisnecessarytoallowtwomoreclockperiods
betweenconversionstoallow39nsofacquisitiontime
for the internal ADC sample-and-hold circuit. With 16
clockperiodsperconversion,themaximumconversion
rateislimitedto2.8Mspstoallow39nsforacquisition
time.Ineithercase,theoutputdatastreamcomesout
withinthefirst16clockperiodstoensurecompatibility
withprocessorserialports.ThedutycycleofCONVcan
bearbitrarilychosentobeusedasaframesyncsignalfor
theprocessorserialport.Asimpleapproachtogenerate
CONVistocreateapulsethatisoneSCKwidetodrivethe
LTC1403-1/LTC1403A-1andthenbufferthissignalwith
theappropriatenumberofinverterstoensurethecorrect
delaydrivingtheframesyncinputoftheprocessorserial
port.ItisgoodpracticetodrivetheLTC1403-1/LTC1403A-1
CONVinputfirsttoavoiddigitalnoiseinterferenceduring
thesample-to-holdtransitiontriggeredbyCONVatthe
startofconversion.Itisalsogoodpracticetokeepthe
widthofthelowportionoftheCONVsignalgreaterthan
15nstoavoidintroducingglitchesinthefrontendofthe
ADCjustbeforethesample-and-holdgoesintoholdmode
attherisingedgeofCONV.
Minimizing Jitter on the CONV Input
Inhighspeedapplicationswherehighamplitudesinewaves
above100kHzaresampled,theCONVsignalmusthave
aslittlejitteraspossible(10psorless).Thesquarewave
outputofacommoncrystalclockmoduleusuallymeets
thisrequirementeasily.ThechallengeistogenerateaCONV
signalfromthiscrystalclockwithoutjittercorruptionfrom
otherdigitalcircuitsinthesystem.Aclockdividerand
anygatesinthesignalpathfromthecrystalclocktothe
CONVinputshouldnotsharethesameintegratedcircuit
withotherpartsofthesystem.Asshownintheinterface
circuitexamples,theSCKandCONVinputsshouldbe
drivenfirst,withdigitalbuffersusedtodrivetheserialport
interface.AlsonotethatthemasterclockintheDSPmay
alreadybecorruptedwithjitter,evenifitcomesdirectly
fromtheDSPcrystal.Anotherproblemwithhighspeed
processorclocksisthattheyoftenusealowcost,low
speedcrystal(i.e.,10MHz)togenerateafast,butjittery,
phase-locked-loopsystemclock(i.e.,40MHz).Thejitter
inthesePLL-generatedhighspeedclockscanbeseveral
nanoseconds.Notethatifyouchoosetousetheframe
syncsignalgeneratedbytheDSPport,thissignalwill
havethesamejitteroftheDSP’smasterclock.
Serial Clock Input (SCK)
TherisingedgeofSCKadvancestheconversionprocess
andalsoudpateseachbitintheSDOdatastream.After
CONVrises,thethirdrisingedgeofSCKstartsclocking
outthe12/14databitswiththeMSBsentfirst.Asimple
approach is to generate SCK to drive the LTC1403-1/
LTC1403A-1 first and then buffer this signal with the
appropriatenumberofinverterstodrivetheserialclock
inputoftheprocessorserialport.Usethefallingedgeof
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