參數(shù)資料
型號: LTC1403CMSE-1#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Serial 12-Bit, 2.8Msps Sampling ADCs with Shutdown; Package: MSOP; No of Pins: 10; Temperature Range: 0°C to +70°C
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PDSO10
封裝: LEAD FREE, PLASTIC, MSOP-10
文件頁數(shù): 22/22頁
文件大?。?/td> 575K
代理商: LTC1403CMSE-1#PBF
LTC1403-1/LTC1403A-1
14031fb
Block Diagram
pin Functions
AIN+ (Pin 1):NoninvertingAnalogInput.AIN+operates
fullydifferentiallywithrespecttoAIN–witha–1.25Vto
1.25VdifferentialswingwithrespecttoAIN–anda0Vto
VDDcommonmodeswing.
AIN– (Pin 2):InvertingAnalogInput.AIN–operatesfully
differentiallywithrespecttoAIN+witha1.25Vto–1.25V
differentialswingwithrespecttoAIN+anda0VtoVDD
commonmodeswing.
VREF (Pin 3):2.5VInternalReference.BypasstoGND
andtoasolidanaloggroundplanewitha10Fceramic
capacitor(or10Ftantaluminparallelwith0.1Fceramic).
Canbeoverdrivenbyanexternalreferencebetween2.55V
andVDD.
GND (Pins 4, 5, 6, Exposed Pad Pin 11):Ground.These
groundpinsandtheexposedpadmustbetieddirectlyto
thesolidgroundplaneunderthepart.Keepinmindthat
analogsignalcurrentsanddigitaloutputsignalcurrents
flowthroughthesepins.
VDD (Pin 7):3VPositiveSupply.Thissinglepowerpin
supplies3Vtotheentirechip.BypasstoGNDandtoa
solidanaloggroundplanewitha10Fceramiccapacitor
(or10Ftantaluminparallelwith0.1Fceramic).Keepin
mindthatinternalanalogcurrentsanddigitaloutputsignal
currentsflowthroughthispin.Careshouldbetakento
placethe0.1FbypasscapacitorasclosetoPins6and
7aspossible.
SDO (Pin 8):Three-StateSerialDataOutput.Eachof
output datawords representsthe differencebetween
AIN+andAIN–analoginputsatthestartoftheprevious
conversion.Theoutputformatis2’scomplement.
SCK (Pin 9):ExternalClockInput.Advancestheconver-
sionprocessandsequencestheoutputdataontherising
edge.RespondstoTTL(≤3V)and3VCMOSlevels.One
ormorepulseswakefromsleep.
CONV(Pin10):ConvertStart.Holdstheanaloginputsignal
andstartstheconversionontherisingedge.Responds
toTTL(≤3V)and3VCMOSlevels.TwopulseswithSCK
infixedhighorfixedlowstatestartNapmode.Fouror
morepulseswithSCKinfixedhighorfixedlowstatestart
Sleepmode.
14031 BD
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC1403A-1
VREF
10F
AIN–
AIN+
14-BIT ADC
3V
10F
14
14-BIT
LA
TCH
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
5
6
11
相關(guān)PDF資料
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