參數(shù)資料
型號(hào)： LSM330DL
廠商： STMICROELECTRONICS
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA28
封裝： 7.50 X 4.40 MM, 1.10 MM HEIGHT, GREEN, PLASTIC, LGA-28
文件頁(yè)數(shù)： 16/54頁(yè)
文件大小： 1064K
代理商： LSM330DL
LSM330DL
Digital interfaces
Doc ID 022018 Rev 1
23/54
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function), the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
Default address
The SDO/SA0 pad can be used to modify the least significant bit of the device address. If
the SA0 pad is connected to a voltage supply, LSb is ‘1’ (ex. address 0011001b), else if the
SA0 pad is connected to ground, the LSb value is ‘0’ (ex address 0011000b).
The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated
START (SR) condition will have to be issued after the two sub-address bytes. If the bit is ‘0’
(Write), the Master will transmit to the slave with the direction unchanged.
Table 17 explain how the SAD+Read/Write bit pattern is composed, listing all the possible
configurations.
Linear acceleration address: the default (factory) 7-bit slave address is
001100xb
Angular rate sensor: the default (factory) 7-bit slave address is 110100xb
Table 16.
Linear acceleration SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SA0
R/W
SAD+R/W
Read
001100
0
1
00110001 (31h)
Write
001100
0
00110000 (30h)
Read
001100
1
00110011 (33h)
Write
001100
1
0
00110010 (32h)
Table 17.
Angular rate SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SA0
R/W
SAD+R/W
Read
110100
0
1
11010001 (D1h)
Write
110100
0
11010000 (D0h)
Read
110100
1
11010011 (D3h)
Write
110100
1
0
11010010 (D2h)
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