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參數(shù)資料
| 型號(hào)： | LP5551SQX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | PowerWise⑩ Technology Compliant Energy Management Unit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC36 |
| 封裝： | LLP-36 |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 3081K |
| 代理商： | LP5551SQX |
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ripple current. Ceramic capacitors are predominately used in
portable systems and have very low ESR and remain capac-
itive up to high frequencies.
The switcher peak - to - peak output voltage ripple in steady
state can be calculated as:
LDO INFORMATION
The LDOs included in the LP5551 provide static supply volt-
ages for various functions in the processor. Use the following
sections to determine loading and external components.
LDO LOADING CAPABILITY
The LDOs in the LP5551 can regulate to a variety of output
voltages, depending on the need of the processor. These
voltages can be programmed through the PWI. Table 1 sum-
marizes the parameters of the LP5551 LDOs.
TABLE 1. LDO Parameters
PWI Register Output voltage range Recommended Maximum
Output Current
100 mA
250 mA
50 mA
Dropout Voltage
(typical)
200 mV
150 mV
200 mV
Typical Load
LDO1 R8
LDO2 R7
LDO3 R2
0.6 V – 2.2 V
1.5 V – 3.3 V
V
OSW
+ 0.05 V
1
0.7 V – 1.35 V
2
1.5 V – 3.3 V
PLL
I/O
Memory/Memory
retention
LDO4 R12
250 mA
150 mV
User defined
1. LDO3 tracks the switching converter output voltage (V
OSW
) plus a 50 mV offset when the LP5551 is in active state.
2. LDO3 regulates at the set memory retention voltage when the LP5551 is in shutdown state.
LDO OUTPUT CAPACITOR
The output capacitor sets a low frequency pole and a high
frequency zero in the control loop of an LDO. The capacitance
and the equivalent series resistance (ESR) of the capacitor
must be within a specified range to meet stability require-
ments. The LDOs in the LP5551 are designed to be used with
ceramic output capacitors. The dielectric should be X5R,
X7R, or comparable material to maintain proper tolerances.
Use the following table to choose a suitable output capacitor:
TABLE 2. Output Capacitor Selection Guide
LDO1
LDO2
LDO3
LDO4
Output Capacitance Range (Recommended Typical Value)
1 μF – 20 μF (2.2 μF)
2 μF – 20 μF (4.7 μF)
0.7 μF – 2.2 μF (1.0 μF)
2 μF – 20 μF (4.7 μF)
ESR range
5 mohm – 500 mohm
5 mohm – 500 mohm
5 mohm– 500 mohm
5 mohm – 500 mohm
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PDF描述 |
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| LPBC4-3 | POWR-BLOKS Distribution/Splicer Blocks and Covers |
| LPBC5-1 | POWR-BLOKS Distribution/Splicer Blocks and Covers |
| LPBC5-2 | POWR-BLOKS Distribution/Splicer Blocks and Covers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP5551SQX/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP5552 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PWI 2.0 and PowerWise Technology Compliant Energy Management Unit |
| LP5552_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PWI 2.0 and PowerWise Technology Compliant Energy Management Unit |
| LP5552TL/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP5552TLEV | 功能描述:電源管理IC開發(fā)工具 LP5552TL EVAL BOARD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
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