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參數(shù)資料
| 型號(hào)： | LP3972SQXA413 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC40 |
| 封裝： | 5 X 5 MM, LLP-40 |
| 文件頁數(shù)： | 14/60頁 |
| 文件大?。?/td> | 1171K |
| 代理商： | LP3972SQXA413 |
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I2C Compatible Interface
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
20207614
I2C START and STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
20207615
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. The
number of bytes that can be transmitted per transfer is unre-
stricted. Each byte of data has to be followed by an acknowl-
edge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH)
during the acknowledge clock pulse. The receiver must pull
down the SDA line during the 9th clock pulse, signifying an
acknowledge. A receiver which has been addressed must
generate an acknowledge after each byte has been received.
After the START condition, a chip address is sent by the I2C
master. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP3972 address is
34h. For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to
which the data will be written. The third byte contains data to
write to the selected register.
I2C CHIP ADDRESS - 7h'34
MSB
ADR6
Bit7
ADR5
Bit6
ADR4
Bit5
ADR3
Bit4
ADR2
Bit3
ADR1
Bit2
ADR0
Bit1
R/W
Bit0
0
1
0
1
0
R/W
21
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LP3972
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP3972SQX-A413 | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3972SQX-A413/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3972SQXA514 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Power Management Unit for Advanced Application Processors |
| LP3972SQX-A514 | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3972SQX-A514/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
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