參數(shù)資料
型號： LP2975AIMMX-3.3/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO8
封裝： MINI, SOP-8
文件頁數(shù)： 7/20頁
文件大?。?/td> 1135K
代理商： LP2975AIMMX-3.3/NOPB
Application Hints (Continued)
C
GS =CISS CRSS
G
GD is the Gate-to-Drain capacitance, which is equal to:
C
GD =CRSS
G
m is the transconductance of the FET. The FET data
sheet specifies forward transconductance (G
fs)
at some
value of drain current (defined as I
D). To find Gm at the
desired value of load current (defined as I
L), use the formula:
G
m =Gfs x(IL /ID)
1/2
Where:
R
L is the load resistance.
ESR is the equivalent series resistance of the output
capacitor.
The term R
L / / ESR is defined as:
(R
L xESR)/(RL + ESR)
It can be seen from these equations that C
EFF varies with RL.
To get the worst-case (maximum) value for C
EFF, use the
maximum value of load current, which also means the mini-
mum value of load resistance R
L. It should be noted that in
most cases, the ESR is the dominant term which determines
the value of R
L / / ESR.
Gate Pin Output Impedance
10003420
Gate Capacitance Pole Frequency (f
pg)
The pole frequency resulting from the Gate capacitance
C
EFF is defined as fpg and can be approximated from:
f
pg . 0.16 / (RO xCEFF)
Where:
R
O is the output impedance of the LP2975 Gate pin which
drives the Gate of the FET. It is important to note that R
O is
a function of input supply voltage (see graph GATE PIN
OUTPUT IMPEDANCE).As shown, the minimum value of
R
O is about 550
@ V
IN = 24V, increasing to about 1.55 k
@ V
IN =3V.
Using the equation for f
pg, a family of curves are provided
showing how f
pg varies with CEFF for several values of RO
(see graph f
pg vs. CEFF):
f
pg vs. CEFF
10003421
As can be seen in the graph, values of C
EFF
in the
500 pF–2500 pF range produce values for f
pg between
40 kHz and 700 kHz. To determine what effect f
pg will have
on stability, the bandwidth of the regulator loop must be
calculated (see next section CROSSOVER FREQUENCY
AND PHASE MARGIN).
Crossover Frequency and Phase Margin
The term f
c will be used to define the crossover frequency of
the regulator loop (which is the frequency where the gain
curve crosses the 0 dB axis). The importance of this fre-
quency is that it is the point where the loop gain goes below
unity, which marks the usable bandwidth of the regulator
loop.
It is the phase margin (or lack of it) at f
c that determines
whether the regulator is stable. Phase margin is defined as
the total phase shift subtracted from 180. In general, a
stable loop requires at least 20-30 of phase margin at f
c.
f
c can be approximated by the following equation (all terms
have been previously defined):
10003423
This equation assumes that no C
F is used and fpg/fc > 1.
If the frequency of the Gate capacitance pole f
pg has been
calculated (previous section), the amount of added phase
shift may now be determined. As shown in the graph below
(see graph PHASE SHIFT DUE TO f
pg), the amount of
added phase shift increases as f
pg approaches fc.
The amount of phase shift due to f
pg that can occur before
oscillation takes place depends on how much added phase
shift is present as a result of the C
OUT pole (see previous
section OUTPUT CAPACITOR).
LP2975
www.national.com
15
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