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參數(shù)資料
| 型號： | LMX2487ESQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7500 MHz, PQCC24 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 5/38頁 |
| 文件大?。?/td> | 419K |
| 代理商： | LMX2487ESQ |
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Symbol
Parameter
Conditions
Value
Typ
Units
Min
Max
PHASE NOISE
L
F1Hz
RF
RF Synthesizer
Normalized Phase Noise
Contribution(Note 6)
RF_CPG = 0
RF_CPG = 1
RF_CPG = 3
RF_CPG = 7
RF_CPG = 15
-202
-204
-206
-210
-210
dBc/Hz
L
F1Hz
IF
IF Synthesizer
Normalized Phase Noise
Contribution
-209
dBc/Hz
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
V
IH
High-Level Input Voltage
V
IL
Low-Level Input Voltage
I
IH
High-Level Input Current V
IH
= V
CC
I
IL
Low-Level Input Current
High-Level Output
Voltage
Low-Level Output
Voltage
MICROWIRE INTERFACE TIMING
Data to Clock Set Up
Time
t
CH
Data to Clock Hold Time See MICROWIRE Input Timing
t
CWH
Clock Pulse Width High
t
CWL
Clock Pulse Width Low
Clock to Load Enable Set
Up Time
t
EW
Load Enable Pulse Width See MICROWIRE Input Timing
1.6
V
CC
0.4
V
V
-1.0
1.0
μA
V
IL
= 0 V
-1.0
1.0
μA
V
OH
I
OH
= -500 μA
V
CC
-0.4
V
V
OL
I
OL
= 500 μA
0.4
V
t
CS
See MICROWIRE Input Timing
25
ns
8
ns
See MICROWIRE Input Timing
25
ns
See MICROWIRE Input Timing
25
ns
t
ES
See MICROWIRE Input Timing
25
ns
25
ns
Note 3:
For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
Note 4:
Refer to table in Section
2.4.2 RF_CPG -- RF PLL
Charge Pump Gain for complete listing of charge pump currents.
Note 5:
In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur
offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate
the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency
= 20 MHz, RF_CPG = 7, DITH = 0, VCO Frequency = 3 GHz, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
Note 6:
Normalized Phase Noise Contribution is defined as: L
(f) = L(f) – 20log(N) – 10log(f
) where L(f) is defined as the single side band phase noise
measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large
enough to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100
kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0, VCO Frequency = 3 GHz.
MICROWIRE INPUT TIMING DIAGRAM
30013975
5
www.national.com
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487ESQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQE | 制造商:Texas Instruments 功能描述:PLL, 7.5GHZ, DUAL, DELTA SIGMA, SMD 制造商:Texas Instruments 功能描述:Delta-Sigma LPower Dual PLL,LMX2487ESQE |
| LMX2487ESQE/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQNOPB | 制造商:National Semiconductor 功能描述:PLL Frequency Synthesizer Dual 5MHz to 7500MHz 24-Pin LLP EP T/R |
| LMX2487ESQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
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