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參數(shù)資料
| 型號： | LMX2487ESQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7500 MHz, PQCC24 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 29/38頁 |
| 文件大小： | 419K |
| 代理商： | LMX2487ESQ |
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2.4 R3 REGISTER
REGISTER
R3
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3
0
C2
1
C1
1
C0
1
ACCESS[3:0]
RF_CPG[3:0]
IF_R[11:0]
2.4.1 IF_R[11:0] -- IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for IF_R is 3.
R Value
3
...
4095
IF_R[11:0]
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
1
.
1
1
.
1
2.4.2 RF_CPG -- RF PLL Charge Pump Gain
This is used to control the magnitude of the RF PLL charge pump in steady state operation.
RF_CPG
Charge Pump State
Typical RF Charge Pump Current at 3
Volts (μA)
95
190
285
380
475
570
665
760
855
950
1045
1140
1235
1330
1425
1520
0
1
2
3
4
5
6
7
8
9
1X
2X
3X
4X
5X
6X
7X
8X
9X
10X
11X
12X
13X
14X
15X
16X
10
11
12
13
14
15
2.4.3 ACCESS -- Register Access word
It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional. The ACCESS
[3:0] bits determine which additional registers need to be programmed. Any one of these registers can be individually programmed.
According to the table below, when the state of a register is in default mode, all the bits in that register are forced to a default state
and it is not necessary to program this register. When the register is programmable, it needs to be programmed through the
MICROWIRE. Using this register access technique, the programming required is reduced up to 37%.
ACCESS Bit
ACCESS[0]
ACCESS[1]
ACCESS[2]
ACCESS[3]
Register Location
R3[20]
R3[21]
R3[22]
R3[23]
Register Controlled
Must be set to 1
R5
R6
R7
The default conditions the registers is shown below:
29
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487ESQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQE | 制造商:Texas Instruments 功能描述:PLL, 7.5GHZ, DUAL, DELTA SIGMA, SMD 制造商:Texas Instruments 功能描述:Delta-Sigma LPower Dual PLL,LMX2487ESQE |
| LMX2487ESQE/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQNOPB | 制造商:National Semiconductor 功能描述:PLL Frequency Synthesizer Dual 5MHz to 7500MHz 24-Pin LLP EP T/R |
| LMX2487ESQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
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