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參數(shù)資料
| 型號： | LMX2487ESQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7500 MHz, PQCC24 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 19/38頁 |
| 文件大小： | 419K |
| 代理商： | LMX2487ESQ |
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Input Impedance Measurement Procedure
The above block diagram shows the test setup used for measuring the input impedance for the LMX2487E. The DC blocking
capacitor used between the input SMA connector and the pin being measured must be changed to a zero Ohm resistor. This
procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the network analyzer, ensure that
the part is powered up, and then measure the input impedance. The network analyzer can be calibrated by using either calibration
standards or by soldering resistors directly to the evaluation board. An open can be implemented by putting no resistor, a short
can be implemented by soldering a zero ohm resistor as close as possible to the pin being measured, and a short can be imple-
mented by soldering two 100 ohm resistors in parallel as close as possible to the pin being measured. Calibration is done with the
PLL removed from the PCB. This requires the use of a clamp down fixture that may not always be generally available. If no clamp
down fixture is available, then this procedure can be done by calibrating up to the point where the DC blocking capacitor usually
is, and then implementing port extensions with the network analyzer. Zero ohm resistor is added back for the actual measurement.
Once the setup is calibrated, it is necessary to ensure that the PLL is powered up. This can be done by toggling the power down
bits (RF_PD and IF_PD) and observing that the current consumption indeed increases when the bit is disabled. Sometimes it may
be necessary to apply a signal to the OSCin pin in order to program the part. If this is necessary, disconnect the signal once it is
established that the part is powered up. It is useful to know the input impedance of the PLL for the purposes of debugging RF
problems and designing matching networks. Another use of knowing this parameter is make the trace width on the PCB such that
the input impedance of this trace matches the real part of the input impedance of the PLL frequency of operation. In general, it is
good practice to keep trace lengths short and make designs that are relatively resistant to variations in the input impedance of the
PLL.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487ESQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQE | 制造商:Texas Instruments 功能描述:PLL, 7.5GHZ, DUAL, DELTA SIGMA, SMD 制造商:Texas Instruments 功能描述:Delta-Sigma LPower Dual PLL,LMX2487ESQE |
| LMX2487ESQE/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQNOPB | 制造商:National Semiconductor 功能描述:PLL Frequency Synthesizer Dual 5MHz to 7500MHz 24-Pin LLP EP T/R |
| LMX2487ESQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
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