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參數(shù)資料
| 型號： | LM9812CCV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | LM9812 30-Bit Color Linear CCD Sensor Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數(shù)： | 36/37頁 |
| 文件大?。?/td> | 479K |
| 代理商： | LM9812CCV |
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In systems with separate analog and digital +5V supplies, all the
supply pins of the LM9812 should be powered by the analog +5V
supply. Each supply input should be bypassed to its respective
ground with a 0.1μF capacitor located as close as possible to the
supply input pin. A single 10μF tantalum capacitor should be
placed near the V
A
supply pin to provide low frequency bypass-
ing.
To minimize noise, keep the LM9812 and all analog components
as far as possible from noise generators, such as switching power
supplies and high frequency digital busses. If possible, isolate all
the analog components and signals (OS, reference inputs and
outputs, V
, AGND) on an analog ground plane, separate from
the digital ground plane. The two ground planes should be tied
together at a single point, preferably the point where the power
supply enters the PCB.
5.2 3V Compatible Digital I/O
If 3V digital I/O operation is desired, the V
pin may be pow-
ered by a separate 3V±10% or 3.3V±10% supply. In this case all
the digital I/O pins (CD0-CD9, D0-D9, MCLK, SYNC, RUN/STOP,
CS, RD, WR, EOC, GLCK, OCLK, and RD PIXELI) will be 3V
compatible. The CCD clock signals (1, 2, RS, TR1 and TR2)
remain 5V outputs, powered by V
. In this case, the V
input
should be bypassed to DGND
with a parallel combination of a
0.1μF capacitor and a 10μF tantalum capacitor.
5.3 Power Down Mode
Setting the Power Down bit to a “1” puts the device in a low power
standby mode. The CCD outputs (1, 2, RS, TR1 and TR2) are
pulled low and the analog sections are turned off to conserve
power. The digital logic will continue to operate if MCLK continues
and SYNC is held high, so for minimum power dissipation MCLK
should be stopped when the LM9812 enters the Power Down
mode. Recovery from Power Down typically takes 50μs (the time
required for the reference voltages to settle to 0.5 LSB accuracy).
6.0 RULES, HINTS, AND COMMON DESIGN PROBLEMS
6.1 Ignore MCLK When Designing a System
While the MCLK input is the master clock for all the LM9812 tim-
ing, it should not be used to predict when other clocks or events
will occur. To get the highest possible timing resolution, the
LM9812 uses double-edged flip flops for many functions. CCD
clock output signals, coefficient clocks, and internal clocks may
change state on the rising or falling edge of MCLK, depending on
the state of MCLK and some internal free running state machines
when the RUN/STOP or SYNC input goes high. Normal process
variations from part to part result in different delays between an
MCLK edge and other events in the LM9812.
For a reliable design, synchronize your system to EOC, GCLK,
and OCLK. These signals are repeatable from device to device.
Do not synchronize your system to MCLK: treat it only as a fre-
quency that sets the pixel rate of the system. If you need to gen-
erate additional CCD timing signals, synchronize them to the
LM9812’s TR and RS outputs.
6.2 Weak Latches On Databus
The D0-D9 databus has weak latches on its output pins to keep
the databus from drifting through the input’s trip point when TRI-
STATED. If the voltage on the input pin is at the threshold, large
amounts of current can be drawn from the digital I/O supply
because the N and the P channel of the input buffer are simulta-
neously on. These latches are very weak (sourcing and sinking
about 50μA typically) and can be easily overdriven.
6.3 Don’t Decrement the Reference Sample Position Regis-
ter by 1
A write to the Reference Sample Position Register (Configuration
Register 22) containing a value that is 1 less than the current
value stored in the Reference Sample Position Register will
sometimes make one of the LM9812’s internal state machines to
fail, causing erratic and improper operation of the LM9812. For
example, if the value currently stored in the Reference Sample
Position Register is 12, then writing an 11 can cause this prob-
lem.
To avoid this condition, never decrement the existing value stored
in the Reference Sample Position Register by 1. Incrementing by
any amount or decrementing by 2 or greater or writing the same
number over again will not cause any problems.
To get out of this mode, write a new number to the Reference
Sample Position Register that is greater than the original number.
Since incrementing and decrementing this register should only be
done during the development phase of the system until an ideal
value for this register is chosen. This issue should cause abso-
lutely no problems in production, since the value of this register
will be fixed, so the firmware should never write more than the
final ideal value to this register.
6.4 Taking RD Low With CS High Will Drive the Databus
In many digital systems, the RD signal is ignored when CS is held
high. This is not the case with the The LM9812. Taking RD low
with CS high will take the D0-D9 databus out of tristate and put
random data on the databus. Do not assume that RD is ignored
when CS is high.
Figure 14: Weak Latches On Databus
10
D0-D9
From
Multiplier
From
Config
Register
To
Config
Register
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