參數(shù)資料
型號: LM4935
廠商: National Semiconductor Corporation
元件分類: ADC
英文描述: Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC
中文描述: 音頻子系統(tǒng)的雙模單聲道立體聲耳機(jī)和揚聲器放大器的高效率和多功能模數(shù)轉(zhuǎn)換器
文件頁數(shù): 56/112頁
文件大小: 5017K
代理商: LM4935
12.0 Status & Control Registers
(Continued)
12.33 GPIO CONFIGURATION REGISTER
This register is used to control the GPIO system.
TABLE 32. GPIO (0x1Ah)
Bits
2:0
Field
Description
GPIO_SEL
This sets the function of the GPIOs when the Audio Interface is not using them.
GPIO_SEL
000
2
001
2
010
2
011
2
100
2
101
2
110
2
111
2
Setting GPIO_SEL = “010” with the GPIO_TEST_MODE bit (register 0X26h) set configures the
GPIOs for digital mic operation. With this setting, GPI01 will output VADC_CLK_OUT to provide a
clock for the digital mic. GPIO2 will accept digital mic data. GPIO1’s LS_AMP_ENABLE setting will
be logic high whenever the loudspeaker amplifier is enabled. This is useful for enabling an external
amplifier for stereo loudspeaker applications.
This field selects the SAR output channel for the 2nd (Right) I
2
S channel or for SAR_SDO via
GPIO2.
SAR_CH_SEL
00
2
01
2
10
2
11
2
If set the I2S operates in left justified mode (sometimes referred to as DSP mode). See example
below. (Note 30)
If set the PCM interface uses LONG frame sync which is essentially an inverted short frame sync.
If GPIO_SEL is set to GPIO_DATA then the content of this field is passed to GPIO1 as an output.
GPIO 1
0
READABLE
LS_AMP_ENABLE
GPIO_DATA
0
READABLE
LS_AMP_ENABLE
GPIO_DATA
GPIO 2
0
SPI_SDO
SPI_SDO
SPI_SDO
SPI_SDO
SAR_SDO
SAR_SDO
SAR_SDO
4:3
SAR_CH_SEL
Selected Channel
VSAR_1
VSAR_2
D_V
DD
/2 or BB_V
DD
A_V
DD
/2
5
I2S_MODE
6
7
PCM_LONG
GPIO_DATA
Note 30:
The left justified I
2
S mode is similar to normal I
2
S other than there is no delay between a change in WS to the MSB:
20134117
FIGURE 12. I
2
S Serial Data Format (Left Justified Mode)
L
www.national.com
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