參數資料
型號: LM12L454CIV
英文描述: IC-SM-12 BIT DAS
中文描述: 集成電路的Sm - DAS的12位
文件頁數: 28/36頁
文件大?。?/td> 538K
代理商: LM12L454CIV
5.0 Analog Considerations
(Continued)
mended for supply bypassing. Separate bypass capacitors
should be used for the V
A
a
and V
D
a
supplies and placed
as close as possible to these pins.
5.8 GROUNDING
The LM12L454/8’s nominal high resolution performance
can be maximized through proper grounding techniques.
These include the use of separate analog and digital ground
planes. The digital ground plane is placed under all compo-
nents that handle digital signals, while the analog ground
plane is placed under all analog signal handling circuitry.
The digital and analog ground planes are connected at only
one point, the power supply ground. This greatly reduces
the occurrence of ground loops and noise.
It is recommended that stray capacitance between the ana-
log inputs or outputs (LM12L454: IN0–IN3, MUXOUT
a
,
MUXOUT
b
, S/H IN
a
, S/H IN
b
; LM12L458: IN0–IN7,
V
REF
a
, and V
REF
b
) be reduced by increasing the clear-
ance (
a
(/16
th inch) between the analog signal and refer-
ence pins and the ground plane.
5.9 CLOCK SIGNAL LINE ISOLATION
The LM12L454/8’s performance is optimized by routing the
analog input/output and reference signal conductors (pins
34–44) as far as possible from the conductor that carries
the clock signal to pin 23. Ground traces parallel to the
clock signal trace can be used on printed circuit boards to
reduce clock signal interference on the analog input/output
pins.
6.0 Application Circuits
6.1 PC EVALUATION/INTERFACE BOARD
Figure 13 is the schematic of an evaluation/interface board
designed to interface the LM12(H)454 or LM12(H)458 with
an XT or AT style computer. The LM12(H)454/8 is the 5V
version of the Data Acquisition System. It is functionally
equivalent to the LM12L454/8. See the LM12(H)454/8 da-
tasheet for further information. The board can be used to
develop both software and hardware for applications using
the LM12L454/8. The board hardwires the BW (Bus Width)
pin to a logic high, selecting an 8-bit wide databus. There-
fore, it is designed for an 8-bit expansion slot on the com-
puter’s motherboard.
The circuit operates on a single
a
5V supply derived from
the computer’s
a
12V supply using an LM340 regulator.
This greatly attenuates noise that may be present on the
computer’s power supply lines. However, your application
may only need an LC filter.
Figure 13 also shows the recommended supply (V
A
a
and
V
D
a
) and reference input (V
REF
a
and V
REF
b
) bypassing.
The digital and analog supply pins can be connected to-
gether to the same supply voltage. However, they need sep-
arate, multiple bypass capacitors. Multiple capacitors on the
supply pins and the reference inputs ensures a low imped-
ance bypass path over a wide frequency range.
All digital interface control signals (IOR, IOW, and AEN),
data lines (DB0–DB7), address lines (A0–A9), and IRQ (in-
terrupt request) lines (IRQ2, IRQ3, and IRQ5) connections
are made through the motherboard slot connector. All ana-
log signals applied to, or received by, the input multiplexer
(IN0–IN7 for the LM12(H)458 and IN0–IN3, MUXOUT
a
,
MUXOUT
b
, S/H IN
a
and S/H IN
b
for the LM12(H)454),
V
REF
a
, V
REF
b
, V
REFOUT
, and the SYNC signal input/
output are applied through a DB-37 connector on the rear
side of the board.Figure 13 shows that there are numerous
analog ground connections available on the DB-37 connec-
tor.
The voltage applied to V
REF
b
and V
REF
a
is selected using
two jumpers, JP1 and JP2. JP1 selects between the voltage
applied to the DB-37’s pin 24 or GND and applies it to the
LM12(H)454/8’s V
REF
b
input. JP2 selects between the
LM12(H)454/8’s internal reference output, V
REFOUT
, and
the voltage applied to the DB-37’s pin 22 and applies it to
the LM12(H)454/8’s V
REF
a
input.
TABLE III. LM12(H)454/8 Evaluation/Interface
Board SW DIP-8 Switch Settings
for Available I/O Memory Locations
Hexidecimal
I/O Memory
Base Address
SW DIP-8
SW1
(SEL0)
SW2
(SEL1)
SW3
(SEL2)
SW4
(SEL3)
100
120
140
160
180
1A0
1C0
300
340
280
2A0
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
The board allows the use of one of three Interrupt Request
(IRQ) lines IRQ2, IRQ3, and IRQ5. The individual IRQ line
can be selected using switches 5, 6, and 7 of SW DIP-8.
When using any of these three IRQs, the user needs to
ensure that there are no conflicts between the evaluation
board and any other boards attached to the computer’s
motherboard.
Switches 1–4, along with address lines A5–A9 are used as
inputs to GAL16V8 Programmable Gate Array (U2). This de-
vice forms the interface between the computer’s control
and address lines and generates the control signals used by
the LM12(H)454/8 for CS, WR, and RD. It also generates
the signal that controls the data buffers. Several address
ranges within the computer’s I/O memory map are avail-
able. Refer to Table III for the switch settings that gives the
desired I/O memory address range. Selection of an address
range must be done so that there are no conflicts between
the evaluation board and any other boards attached to the
computer’s motherboard. The GAL equations are shown in
Figure 14. The GAL functional block diagram is shown in
Figure 15.
Figures 16–19 show the layout of each layer in the 3-layer
evaluation/interface board plus the silk-screen layout show-
ing parts placement.Figure 17 is the top or component side,
Figure 18 is the middle or ground plane layer, Figure 19 is
the circuit side, and Figure 16 is the parts layout.
28
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