參數(shù)資料
型號: LM12L454CIV
英文描述: IC-SM-12 BIT DAS
中文描述: 集成電路的Sm - DAS的12位
文件頁數(shù): 19/36頁
文件大小: 538K
代理商: LM12L454CIV
2.0 Internal User-Programmable Registers
(Continued)
A4 A3 A2 A1
Purpose
Type D15 D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
to
1
0
Instruction RAM
(RAM Pointer
e
00)
R/W
Acquisition
Time
Watch-
dog
V
IN
b
V
IN
a
0
8/12 Timer Sync
(MUXOUT
b
)
*
(MUXOUT
a
)
*
Pause Loop
1
1
0
0
to
1
0
Instruction RAM
(RAM Pointer
e
01)
R/W
0
Don’t Care
l
/
k
Sign
Limit
Y
1
1
1
0
0
to
1
0
Instruction RAM
(RAM Pointer
e
10)
R/W
0
Don’t Care
l
/
k
Sign
Limit
Y
2
1
1
1
0
0
0
Configuration
Register
R/W
Don’t Care
DIAG
2
Test
RAM
Pointer
I/O
Sel
Auto
Zero
ec
Mask
Chan Stand-
Full
CAL
Auto-
Zero
Reset Start
e
0
by
Interrupt Enable
Register
R/W
Number of Conversions
in Conversion FIFO
to Generate INT2
Sequencer
Address to
Generate INT1
INT7
Don’t
Care
INT5
INT4
INT3
INT2
INT1
INT0
1
0
0
1
Address
of
Sequencer
Instruction
being
Executed
R
Actual Number of
Conversion Results
in Conversion FIFO
INST7
‘‘0’’
INST5 INST4 INST3 INST2 INST1 INST0
1
0
1
0
Interrupt Status
Register
1
0
1
1
Timer
Register
R/W
Timer Preset High Byte
Timer Preset Low Byte
1
1
0
0
Conversion
FIFO
R
Address
or Sign
Sign
Conversion
Data: MSBs
Conversion Data: LSBs
1
1
0
1
Limit Status
Register
R
Limit
Y
2: Status
Limit
Y
1: Status
*
LM12L454 (Refer to Table II).
2
LM12L458 only. Must be set to ‘‘0’’ for the LM12L454.
FIGURE 9. LM12L454/8 Memory Map for 16-Bit Wide Databus (BW
e
‘‘0’’, Test Bit
e
‘‘0’’ and A0
e
Don’t Care)
19
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