參數(shù)資料
型號(hào): LM1276AAA/NA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 音頻/視頻放大
英文描述: 1 CHANNEL, VIDEO PREAMPLIFIER, PDIP28
封裝: PLASTIC, DIP-28
文件頁(yè)數(shù): 25/50頁(yè)
文件大小: 6075K
代理商: LM1276AAA/NA
Control Register Definitions
OSD INTERFACE REGISTERS
Frame Control Register 1:
FRMCTRL1 (0x8400)
Autosize
done
Autosize
Fade I/
O
Trans
Clear
Win2
Win1
OSD
ASZDN
ASZEN
FEN
TD
CDPR
D2E
D1E
OSE
Bit 0
On-Screen Display Enable. The On-Screen Display will be disabled when this bit is a zero. When this bit is a one the
On-Screen Display will be enabled. This controls both Window 1 and Window 2.
Bit 1
Display Window 1 Enable. When this bit and Bit 0 of this register are both ones, Display Window 1 is enabled. If either
bit is a zero, then Display Window 1 will be disabled.
Bit 2
Display Window 2 Enable. When this bit and Bit 0 of this register are both ones, Display Window 2 is enabled. If either
bit is a zero, then Display Window 2 will be disabled.
Bit 3
Clear Display Page RAM. Writing a one to this bit will result in setting all of the Display Page RAM values to zero. This
bit is automatically cleared after the operation is complete. This bit is initially asserted by default at power up, and will
clear itself back to zero shortly after. Thus, the default value is one only momentarily, and then will remain zero until
manually asserted again or until the power is cycled.
Bit 4
Transparent Disable. When this bit is a zero, a palette color of black (i.e., color palette look-up table value of 0x00) in
the first 8 palette look-up table address locations (i.e., ATT0–ATT7) will be interpreted as transparent. When this bit is
a one, the color will be interpreted as black.
Bit 5
Fade In/Out Enable. When this bit is a 1, the OSD Fade In/Fade Out function is enabled. When this bit is a 0, the function
is disabled.
Bit 6
Auto Size Enable. When this bit is a 1, the Auto Size function is enabled. Once video detection and measurement is
completed, the bit will automatically clear itself back to 0.
Bit 7
Auto Size Done. When the device has completed Auto Size calculations, this bit will automatically be set high by the
chip to indicate to the MCU that the Auto Size data registers are valid and available. This bit is automatically cleared
when the MCU sets the ASZEN bit (0x8400[6]), or when the device programs a calibration sequence for the Windows
HiBrite software.
Frame Control Register 2:
FRMCTRL2 (0x8401)
Pixels per Line
Blink Period
PL[2:0]
BP[4:0]
Bits 4–0
Blink Period. These five bits set the blink period of the blinking feature, which is determined by mulitiplying the value of
these bits by 8, and then multiplying the result by the vertical field rate.
Bits 7–5
Pixels per Line. These three bits determine the number of pixels per line of OSD characters. See Table 23, which gives
the maximum horizontal scan rate. Also see Table 2.
TABLE 23. OSD Pixels per Line
Bits 7–5
Description
Max Horizontal Frequency (kHz)
0x0
704 pixels per line
110
0x1
768 pixels per line
110
0x2
832 pixels per line
110
0x3
896 pixels per line
110
0x4
960 pixels per line
110
0x5
1024 pixels per line
108
0x6
1088 pixels per line
102
0x7
1152 pixels per line
96
31
www.national.com
200969 Version 2 Revision 4
Print Date/Time: 2011/07/11 11:20:12
LM1276
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